SMH4803AS View Datasheet(PDF) - Summit Microelectronics
Part Name
Description
MFG CO.
'SMH4803AS' PDF : 19 Pages View PDF
SMH4803A
Preliminary
PRODUCT DESCRIPTION
The SMH4803A is an integrated solution for high reliability
systems to monitor and react to events that could have a
detrimental effect on a system. It can contain or limit faults
to a single circuit board before that fault propagates to the
system. Its programmability lets a single board satisfy
multiple circuit demands while customized to meet special
requirements.
The SMH4803A monitors and controls the primary voltage
in a distributed power system while providing for both hot-
swapping and secondary voltage sequencing in multi-
supply systems. The primary power source can be shut
down if events are sensed that could result in damage to
either the circuit board or the system supply. An external
FET switch is used to soft start the primary voltage once
normal operating conditions are met. The external FET
also uses an external shunt to monitor current for the
circuit breaker function.
The SMH4803A sequences secondary voltage by timed
or externally controlled outputs that enable DC/DC con-
verters. Its reference voltages provide isolation between
primary and secondary voltages, but allow expansion of its
features.
PIN CONFIGURATION
20-Pin SOIC
DRAIN SENSE 1
20 VDD
VGATE 2
19 PG2#
EN/TS 3
18 PG1#
PD1# 4
17 PG3#
PD2# 5
16 ENPGA
FAULT# 6
15 ENPGB
RESET# 7
14 2.5VREF
MODE 8
13 5.0VREF
CBSENSE 9
12 OV
VSS 10 11 UV
2051 PCon 1.0
PIN DESCRIPTIONS
DRAIN SENSE (1)
The DRAIN SENSE input monitors the voltage at the drain
of the external power MOSFET switch with respect to VSS.
An internal 10µA source pulls the DRAIN SENSE signal
towards the 5V reference level. DRAIN SENSE must be
held below 2.5V to enable the PG outputs.
VGATE (2)
The VGATE output activates an external power MOSFET
switch. This signal supplies a constant current output
(100µA typical), which allows easy adjustment of the
MOSFET turn on slew rate.
EN/TS (3)
The Enable/Temperature Sense input is the master en-
able input. If EN/TS is less than 2.5V, VGATE will be
disabled. This pin has an internal 200kΩ pull-up to 5V.
FAULT# (6)
This is an open-drain, active-low output that indicates the
fault status of the device.
RESET# (7)
Reset# is used to clear latched fault conditions. When this
pin is held low the VGATE and PG outputs are disabled.
Refer to the Circuit Breaker Operation and the associated
timing diagrams for detailed characteristics. This pin has
an internal 50kΩ pull-up to 5V.
MODE (8)
The state of the MODE signal determines how fault
conditions are cleared. The device is in the latched mode
when the signal is held at VSS, and the cycle mode when
held at 5V or left floating. This pin has an internal 50kΩ
pull-up to 5V.
PD1# and PD2# (4 & 5)
These are logic level active low inputs that can optionally
be employed to enable VGATE and the PG outputs when
they are at VSS. These pins each have an internal 50kΩ
pull-up to 5V.
CBSENSE (9)
The circuit breaker sense input is used to detect over-
current conditions across an external, low value sense
resistor (RS) tied in series with the Power MOSFET. A
voltage drop of greater than 50mV across the resistor for
longer than tCBD will trip the circuit breaker. A program-
mable Quick-Trip™ sense point is also available.
SUMMIT MICROELECTRONICS, Inc.
2051 4.4 3/15/01
3
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