SMH4804 View Datasheet(PDF) - Summit Microelectronics
Part Name
Description
MFG CO.
'SMH4804' PDF : 41 Pages View PDF
Register 8 - Address 1000
This register is used to control the I2C bus interface activity. Bit 3 determines the Device Type Address, bits 2
and 1 select the register access capability, and bit 0 determines whether the device must receive a bus address
that corresponds to the biasing of the address pins.
Note: If the fault latch option is selected and write access is denied the SMH4804 cannot be cleared of a fault
condition.
Bits
Default R/W
Description
3210
0
When bit 3 is cleared, the device type address is 1011.
0b0 R/W
1
When bit 3 is set, the device type address is 1010.
00
When bits 2:1 are set to 0b00, the Configuration registers are
read/write (R/W).
01
10
11
0b00
When bits 2:1 are set to 0b01, the Configuration registers are
R/W read-only (RO).
When bits 2:1 are set to 0b10 or 0b11, I2C access to the
Configuration registers is disabled.
0
When bit 0 is cleared, the SMH4804 responds to all address
pins.
0b1 R/W
1
When bit 0 is set, the SMH4804 responds to the address set by
the address pin pin polarities (A0,A1 and A2).
Table 9. Register 8 Bitmap
37
Summit Microelectronics
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