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SN260 View Datasheet(PDF) - STMicroelectronics

Part Name
Description
MFG CO.
SN260
ST-Microelectronics
STMicroelectronics ST-Microelectronics
'SN260' PDF : 88 Pages View PDF
SN260
5.11
Functional description
Random number generator
The SN260 allows for the generation of random numbers by exposing a randomly generated
bit from the RX ADC. Analog noise current is passed through the RX path, sampled by the
receive ADC, and stored in a register. The value contained in this register could be used to
seed a software-generated random number. The EmberZNet stack utilizes these random
numbers to seed the random MAC backoff and encryption key generators.
5.12
Watchdog timer
The SN260 contains an internal watchdog timer clocked from the internal oscillator. If the
timer reaches its time-out value of approximately 2 seconds, it will reset the SN260. This
reset signal cannot be routed externally to the Host.
The SN260 firmware will periodically restart the watchdog timer while the firmware is
running normally. The Host cannot effect or configure the watchdog timer.
5.13
Sleep timer
The 16-bit sleep timer is contained in the always-powered digital block. The clock source for
the sleep timer is a calibrated 1kHz clock. The frequency is slowed down with a 2N prescaler
to generate a final timer resolution of 1ms. With a 1ms tick and a 16-bit timer, the timer
wraps about every 65.5 seconds. The EmberZNet stack appropriately handles timer wraps
allowing the Host to order a theoretical maximum sleep delay of 4 million seconds.
5.14
Power management
The SN260 supports four different power modes: active, idle, deep sleep, and power down.
Active mode is the normal, operating state of the SN260.
While in idle mode, code execution halts until any interrupt occurs. All modules of the SN260
including the radio continue to operate normally. The EmberZNet stack automatically
invokes idle as appropriate.
Deep sleep mode and power down mode both power off most of the SN260, including the
radio, and leave only the critical chip functions powered. The internal regulator is disabled
and VREG_OUT is turned off. All output signals are maintained in a frozen state. Upon
waking from deep sleep or power down mode, the internal regulator is re-enabled. Deep
sleep and power down result in the same sleep current consumption. The two sleep modes
differ as follows: the SN260 can wake on both an internal timer and an external signal from
deep sleep mode; power down mode can only wake on an external signal.
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