SPC5607BECLLR View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
'SPC5607BECLLR' PDF : 92 Pages View PDF
Package pinouts
2.3 208MAPBGA pin configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PC[8] PC[1 PH[1 PJ[4] PH[8] PH[4] PC[5] PC[0] PI[0] PI[1] PC[2] PI[4] PE[1 PH[1 NC NC
A
3] 5]
5] 1]
A
PC[9] PB[2] PH[1 PC[1 PE[6] PH[5] PC[4] PH[9] PH[1 PI[2] PC[3] PG[1 PG[1 PG[1 PA[1 PA[1
B
3] 2]
0]
1] 5] 4] 1] 0] B
PC[14 VDD_ PB[3] PE[7] PH[7] PE[5] PE[3] VSS_ PC[1] PI[3] PA[5] PI[5] PE[1 PE[1 PA[9] PA[8]
C
]
HV
LV
4] 2]
C
PH[14 PI[6] PC[1 PI[7] PH[6] PE[4] PE[2] VDD VDD NC PA[6] PH[1 PG[1 PF[1 PE[1 PA[7]
D
]
5]
_LV _HV
2] 0] 4] 3]
D
PG[4] PG[5] PG[3] PG[2]
E
PG[1] PG[0] PF[1 VDD
5] _HV E
F PE[0] PA[2] PA[1] PE[1]
PH[0] PH[1] PH[3] PH[2] F
PE[9] PE[8] PE[1 PA[0]
G
0]
VSS_ VSS_ VSS_ VSS_
HV HV HV HV
VDD PI[12 PI[13 MSE
_HV ]
]
OG
VSS_ PE[1 VDD NC
H HV 1] _HV
VSS_ VSS_ VSS_ VSS_
HV HV HV HV
MDO MDO MDO MDO
3
2
0
1H
RESE VSS_ NC NC
JT
LV
VSS_ VSS_ VSS_ VSS_
HV HV HV HV
PI[8] PI[9] PI[10 PI[11
]
]J
EVTI NC VDD VDD
_BV _LV
K
VSS_ VSS_ VSS_ VSS_
HV HV HV HV
VDD PG[1 PA[3] PG[1
_HV_ 2]
ADC
3]
K
1
PG[9] PG[8] NC EVT
L
O
PB[1 PD[1 PD[1 PB[1
5] 5] 4] 4] L
PG[7] PG[6] PC[1 PC[1
M
0] 1]
PB[1 PD[1 PD[1 PB[1
3] 3] 2] 2] M
PB[1] PF[9] PB[0] VDD PJ[0] PA[4] VSS_ EXTA VDD PF[0] PF[4] VSS_ PB[1 PD[1 PD[9] PD[1
_HV
LV L _HV
HV_ 1] 0]
1]
N
ADC
N
1
PF[8] PJ[3] PC[7] PJ[2] PJ[1] PA[1 VDD XTAL PB[1 PF[1] PF[5] PD[0] PD[3] VDD PB[6] PB[7]
4] _LV
0]
_HV_
P
ADC
P
0
PF[12 PC[6] PF[1 PF[1 VDD PA[1 PA[1 PI[14 XTAL PF[3] PF[7] PD[2] PD[4] PD[7] VSS_ PB[5]
]
R
0] 1] _HV 5] 3] ]
HV_
ADC
R
0
NC NC NC MCK NC PF[1 PA[1 PI[15 EXTA PF[2] PF[6] PD[1] PD[5] PD[6] PD[8] PB[4]
T
O
3] 2]
]
L
T
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
NOTE: The 208 MAPBGA is available only as development package for Nexus 2+.
NC = Not connected
Figure 4. 208 MAPBGA configuration
MPC5607B Microcontroller Data Sheet, Rev. 3
10
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
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