SPC5607BECLLR View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
'SPC5607BECLLR' PDF : 92 Pages View PDF
Electrical characteristics
Table 9. Recommended operating conditions (5.0 V) (continued)
Symbol
Parameter
Conditions
Value
Unit
Min
Max
VDD_ADC5 SR Voltage on VSS_HV_ADC0, VSS_HV_ADC1 (ADC
—
4.5
reference) with respect to ground (VSS)
Voltage drop2
3.0
5.5 V
5.5
VIN
IINJPAD
SR Voltage on any GPIO pin with respect to ground (VSS)
SR Injected input current on any pin during overload
condition
Relative to VDD VDD-0.1 VDD+0.1
—
VSS-0.1
-
V
Relative to VDD
-
VDD+0.1
—
-5
5 mA
IINJSUM
TVDD
SR Absolute sum of all injected input currents during
overload condition
SR VDD slope to ensure correct power up6
—
-50
50
—
—
0.25 V/µs
—
3
— V/s
TA C-Grade SR Ambient temperature under bias
Part
fCPU < 64 MHz −40
85 °C
TJ C-Grade SR Junction temperature under bias
Part
—
−40
110
TA V-Grade SR Ambient temperature under bias
Part
fCPU < 64 MHz −40
105
TJ V-Grade SR Junction temperature under bias
Part
—
−40
130
TA M-Grade SR Ambient temperature under bias
Part
fCPU < 60 MHz −40
125
TJ M-Grade SR Junction temperature under bias
—
−40
150
Part
1 100 nF capacitance needs to be provided between each VDD/VSS pair
2 Full device operation is guaranteed by design when the voltage drops below 4.5V down to 3.6V. However, certain
analog electrical characteristics will not be guaranteed to stay within the stated limits.
3 330 nF capacitance needs to be provided between each VDD_LV/VSS_LV supply pair
4 470 nF capacitance needs to be provided between VDD_BV and the nearest VSS_LV (higher value may be needed
depending on external regulator characteristics). This decoupling need to be increased as recommended in
Section 3.5.1, “External ballast resistor recommendations incase external ballast resistor is planned to be used.
5 100 nF capacitance needs to be provided between VDD_ADC/VSS_ADC pair
6 Guaranteed by device validation
NOTE
RAM data retention is guaranteed wi‘th VDD_LV not below 1.08 V.
MPC5607B Microcontroller Data Sheet, Rev. 3
16
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
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