SPEAR300-2 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

SPEAR300-2

Embedded MPU with ARM926 core, flexible memory support, powerful connectivity features and human machine interface

STMicroelectronics 

Prev 61 62 63 64 65 66 67 68 69 70 Next

SPEAr300

6.2.2

CLCD timing characteristics divided clock

Figure 15. CLCD waveform with CLCP divided

CLCP

Tclock

Tmax

Timing requirements

Tmin

CLD[23:0],CLAC,CLLE,CLLP,

CLFP ,CLPOWER

Tstabl e

Tf

Tr

Figure 16. CLCD block diagram with CLCP divided

t1

CLCDCLK

D Q SET

Q CL R

D Q SET

CLD[23:0],CLAC,CLLE,

CLLP,CLFP,CLPOWER

t2

CLCP

t3

Q CL R

Table 105.

Table 30. CLCD timings with CLCP divided

Parameter

Value

tCLOCK divided max

tCLOCK divided max rise (tr)

tCLOCK divided max (tf)

tmin

tmax

tSTABLE

12 ns

0.81 ns

0.87 ns

-0.49 ns

2.38 ns

9.13 ns

Frequency

83.3 MHz

Note: 1 tSTABLE = tCLOCK direct max - (tmax + tmin)

2 For tmax the maximum value is taken from the worst case and for tmin the minimum value is

taken from the best case.

3 CLCP should be delayed by {tmax + [tCLOCK direct max - (tmax + tmin)]/2} = 6.945 ns

Doc ID 16324 Rev 2

61/83

Share Link: