SPT5420SIM View Datasheet(PDF) - Signal Processing Technologies
Part Name
Description
MFG CO.
'SPT5420SIM' PDF : 7 Pages View PDF
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1
Supply Voltages
VCC ........................................................................... +6 V
VDD ......................................................................... +15 V
VSS ......................................................................... –15 V
Input Voltages
VREFT ....................................... VSS –0.3 V to VDD +0.3 V
VREFB ...................................... VDD +0.3 V to VSS –0.3 V
Digital Inputs .................................. –0.3 V to VCC +0.3 V
Output Currents
10 mA per Output Channel
Temperature
Operating Temperature ............................. –40 to +85 °C
Storage .................................................... –65 to +150 °C
Note: 1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied
conditions in typical applications.
ELECTRICAL SPECIFICATIONS
TA = TMIN to TMAX, VCC = +5.0 V, VDD = +11.5 V, VSS = –8.0 V, VREFT=3.5 V, VREFB=–1.5 V, RL = +10 kΩ, CL = 50 pF, unless otherwise specified.
TEST
TEST
SPT5420
PARAMETERS
CONDITIONS
LEVEL MIN
TYP
MAX UNITS
Accuracy
Resolution
V
13
Integral Linearity Error (ILE)
VI
±0.5
Differential Linearity Error (DLE)
VI
±0.3
Zero-Scale Error
VREFT = 3.5 V, VREFB = –1.5 V
VI
Full Scale Error
VREFT = 3.5 V, VREFB = –1.5 V
VI
Gain Error
VI
Bits
±2 LSB
±1 LSB
±20 mV
±20 mV
±20 mV
Reference Inputs
DC Input Resistance
Input Current
VREFT1
VREFB2
IV
IV
VI
0
VI
–5.0
100
+3.5
–1.5
MΩ
±1 µA
+5.0 V
0V
RGND Inputs
DC Input Impedance
Input Range
V
IV
–2.0
60
kΩ
2.0 V
Output Characteristics
Output Swing3,4
Short Circuit Current
Resistive Load
Capacitive Load5
DC Output Impedance
VI
+7/–3
V
IV
4
15 mA
VI
5
kΩ
VI
50 pF
IV
0.5 Ω
Digital Inputs
Logic 1 Voltage
Logic 0 Voltage
Maximum Input Current
Input Capacitance
VI
2.4
VI
VI
–10
V
V
0.8 V
10 µA/pin
10 pF
Notes:
1. VREFT < 8 V + (VSS x 0.5); e.g., if VSS = –8 V, then VREFT < 4 V
2. VREFB > (VDD x 0.5) – 9.5 V; e.g., if VDD = 11 V, then VREFB > –4 V
3. VSS + 2.5 V ≤ VOUT ≤ VSS + 16.0 V for 18.5 V ≤ VDD – VSS ≤ 20.0 V
VSS + 2.5 V ≤ VOUT ≤ VDD – 2.5 V for VDD – VSS ≤ 18.5 V
INPUT CODE
4. VOUT = 2 x (VREFB +[VREFT – VREFB] x
8192
) – VRGND
5. Output can drive 10,000 pF without oscillation, but with settling time degradation.
SPT
2
SPT5420
10/11/00
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