Figure 4 - Single Shot Mode Timing Diagram
tSC
Start Convert
Latch
MSB
Clock
1
2
3
4
5
6
7
8
9
10
11
12
A
A
A
A
A
A
A
A
A
A
A
A
Serial Data Out
Start
Conversion
Sample
Analog Input
A7
A6
A5
A4
A3
A2
A1 A0
MSB
LSB
High Z State
Figure 5 - Synchronous Mode Timing Diagram
tSC
Start Convert
Latch
MSB
tSC
Latch
MSB
Clock
Serial Data Out
1
A
Start
2
3
4
5
6
7
8
11
12
A
A
A
A
A
A
A
A
A
Sample
Analog Input
A
A7
A6
A5
A4
A1 A0
High Z State
MSB
LSB
1
2
3
4
5
B
B
B
B
B
Sample
Analog Input
B
B7
MSB
Figure 6 - Free Run Mode Timing Diagram
Start Convert
Latch
MSB
Clock
Serial Data Out
1
2
3
4
5
6
7
8
1
1
1
2
3
4
5
6
7
A
A
A
A
A
A
A
A
1
2
B
B
B
B
B
B
B
A
A
Start
Sample
Analog Input
A
A7
A6
A5
A4
A1 A0
MSB
LSB
B7
B6
B5
Sample
Analog Input
B
MSB
Figure 7 - Typical Interface Circuit
VREF+
0V
REF IN
.01 µF
VIN
VREF+
VDD
Analog In
Data Out
+VDD
.01 µF
Figure 8 - Data Output Timing
td=8 ns
td=8 ns
td=8 ns td=8 ns
+VDD
Clock
4
A
5
1
A
1
1
2
0V
A
A
VREF-
Ground
Clock
SC
+VDD
0V
+VDD
0V
Data Out
A7
MSB
A1
A0
LSB
SPT7730
6
12/19/97