SSM2160 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'SSM2160' PDF : 16 Pages View PDF
SSM2160/SSM2161
Timing Characteristics
Timing
Symbol
Description
Min
Typ
Max
Units
tCL
Input Clock Pulse Width, Low
200
ns
tCH
Input Clock Pulse Width, High
200
ns
tDS
Data Setup Time
50
ns
tDH
Data Hold Time
75
ns
tCW
Positive CLK Edge to End of Write
100
ns
tWC
Write to Clock Setup Time
50
ns
tLW
End of Load Pulse to Next Write
50
ns
tWL
End of Write to Start of Load
50
ns
tL
Load Pulse Width
250
ns
tW3
Load Pulse Width (3-Wire Mode)
250
ns
NOTES
1. An idle HI (CLK-HI) or idle LO (CLK-LO) clock may be used. Data is latched on the negative edge.
2. For SPI or microwire three-wire bus operation, tie LD to WRITE, and use WRITE pulse to drive both pins. (This generates an automatic internal load signal.)
3. If an idle HI clock is used, tCW and tWL are measured from the final negative transition to the idle state.
4. The first data byte selects an address (MSB HI), and subsequent MSB LO states set gain/attenuation levels. Refer to the Address/Data Decoding Truth Table.
5. Data must be sent MSB first.
0
CLK
1
1
DATA
0
1
WRITE
0
1
LD
0
D7
D6
D5
D4
D3
D2
D1
D0
1
CLK
0
1
DATA
0
1
WRITE
0
1
LD
0
tCH
tDS
D7
MSB
tWC
tCL
tDH
Figure 1. Timing Diagrams
tCW
tL
tWL
tLW
REV. 0
–3–
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