SSM2160 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'SSM2160' PDF : 16 Pages View PDF
SSM2160/SSM2161
SSM2160 SSM2161
Pin No. Pin No. Name
1
1
V+
2
2
AGND
3
3
VREF
4
4
5
5
6
6
7
7
8
–
9
–
10
8
11
9
12
10
13
11
14
12
15
13
16
–
17
–
18
14
19
15
20
16
21
17
22
18
CH1 OUT
CH1 IN
CH3 OUT
CH3 IN
CH5 OUT
CH5 IN
WRITE
LD
V–
DGND
CLK
DATA
CH6 IN
CH6 OUT
CH4 IN
CH4 OUT
CH2 IN
CH2 OUT
MSTR SET
23
19
24
20
MSTR OUT
CH SET
PIN DESCRIPTIONS
Function
V+ is the positive power supply pin. Refer to the Power Supply Connections section for more
information.
AGND is the internal ground reference for the audio circuitry. When operating the SSM2160
from dual supplies, AGND should be connected to ground. When operating from a single
supply, AGND should be connected to VREF, the internally generated voltage reference. AGND
may also be connected to an external reference. Refer to the Power Supply Connections section
for more details.
VREF is the internally generated ground reference for the audio circuitry obtained from a buffered
divider between V+ and V–. In a dual-supply application with the AGND pin connected to
ground, VREF should be left floating. In a single supply application, VREF should be connected to
AGND. Refer to the Power Supply Connections section for more details.
Audio Output from Channel 1.
Audio Input to Channel 1.
Audio Output from Channel 3.
Audio Input to Channel 3.
Audio Output from Channel 5.
Audio Input to Channel 5.
A logic LOW voltage enables the SSM2160 to receive information at the DATA input (Pin 15).
A logic HIGH applied to WRITE retains data at their previous settings. See Timing Diagrams.
Serves as CHIP SELECT.
Loads the information retained by WRITE into the SSM2160 at logic LOW. See Timing
Diagrams.
V– is the negative power supply pin. Connect to ground if using in a single supply application.
Refer to the Power Supply Connections section for more details.
DGND is the digital ground reference for the SSM2160. This pin should always be connected to
ground. All digital inputs, including WRITE, LD, CLK, and DATA are TTL input compatible;
drive currents are returned to DGND.
CLK is the clock input. It is positive edge triggered. See Timing Diagrams.
Channel and Master control information flows MSB first into the DATA pin. Refer to Address/
Data Decoding Truth Table, Figure 19, for information on how to control the VCAs.
Audio Input to Channel 6.
Audio Output from Channel 6.
Audio Input to Channel 4.
Audio Output from Channel 4.
Audio Input to Channel 2.
Audio Output from Channel 2.
MSTR SET is connected to the inverting input of an I-V converting op amp used to generate a
Master Control voltage from the Master Control DAC current output. A resistor connected
from MSTR OUT to MSTR SET reduces the step size of the Master control. See the Adjusting
Step Sizes section for more details. A 10 µF capacitor should be connected from MSTR OUT to
MSTR SET to eliminate the zipper noise in the Master control.
MSTR OUT is connected to the output of the I-V converting op amp. See MSTR SET
description.
The step size of the Channel Control can be increased by connecting a resistor from CH SET to
V+. No connection to CH SET is required if the default value of 1 dB per step is desired. Mini-
mum of 10 Ω external resistor. See the Adjusting Step Sizes section for more details.
REV. 0
–5–
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