SST89V554RC-25-C-PI View Datasheet(PDF) - Silicon Storage Technology
Part Name
Description
MFG CO.
'SST89V554RC-25-C-PI' PDF : 62 Pages View PDF
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
SPI Control Register (SPCR)
Location
7
6
D5H
SPIE
SPE
5
DORD
4
MSTR
3
CPOL
2
CPHA
1
SPR1
0
Reset Value
SPR0 00000100b
Symbol
SPIE
SPE
DORD
MSTR
CPOL
CPHA
SPR1, SPR0
Function
If both SPIE and ES are set to one, SPI interrupts are enabled.
SPI enable bit.
0: Disables SPI.
1: Enables SPI and connects SS#, MOSI, MISO, and SCK to pins P1[4], P1[5], P1[6], P1[7].
Data Transmission Order.
0: MSB first in data transmission.
1: LSB first in data transmission.
Master/Slave select.
0: Selects Slave mode.
1: Selects Master mode.
Clock Polarity
0: SCK is low when idle (Active High).
1: SCK is high when idle (Active Low).
Clock Phase control bit.
0: Shift triggered on the leading edge of the clock.
1: Shift triggered on the trailing edge of the clock.
SPI Clock Rate Select bits. These two bits control the SCK rate of the device
configured as master. SPR1 and SPR0 have no effect on the slave. The relationship
between SCK and the oscillator frequency, fOSC, is as follows:
SPR1
0
0
1
1
SPR0
0
1
0
1
SCK = fOSC divided by
4
16
64
128
SPI Status Register (SPSR)
Location
7
6
5
4
3
2
1
0
Reset Value
AAH
SPIF
WCOL
-
-
-
-
-
-
00xxxxxxb
Symbol
SPIF
WCOL
Function
Upon completion of data transfer, this bit is set to 1. If SPIE =1 and ES =1, an interrupt
is then generated. To clear, read SPSR and then access SPDR.
Set if the SPI data register is written to during data transfer. To clear, read SPSR and
then access SPDR.
©2001 Silicon Storage Technology, Inc.
24
S71207-00-000 9/01 555
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