SST89V564RC-40-C-NI View Datasheet(PDF) - Silicon Storage Technology
Part Name
Description
MFG CO.
'SST89V564RC-40-C-NI' PDF : 62 Pages View PDF
FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Preliminary Specifications
8.2.2 16-Bit Software Timer Mode
In the 16-bit Software Timer mode the PCA timer/counter
value is compared with the 16-bit value pre-loaded into the
module’s compare registers (CCAPnH & CCAPnL). When
a match occurs, the event flag (CCFn) is set and an inter-
rupt is generated if ECCFn is set.
8.2.3 High Speed Output Mode
In the High Speed Output mode, the PCA timer/counter is
compared with the 16-bit value pre-loaded into the module’s
compare registers (CCAPnH & CCAPnL). When a match
occurs, the modules corresponding output pin is toggled.
Additionally the event flag (CCFn) is set and an interrupt is
generated if ECCFn is set. The frequency of the output is
only dependent on the PCA timer/counter and will be the
same for all 5 modules but the duty cycle can vary depend-
ing on the value pre-loaded into the compare registers.
8.2.4 Pulse Width Modulator
The Pulse Width Modulator mode generates 1-bit PWMs
by comparing the low byte of the PCA timer (CL) with the
low byte of the compare registers (CCAPnL). When CL <
CCAPnL the corresponding output pin is low. When CL >
CCAPnL the corresponding output pin is high. The fre-
quency of the PWM is only dependent on the PCA timer/
counter and will be the same for all 5 modules. The duty
cycle will vary depending on the value in CCAPnL.
CCAPnL can be changed dynamically by loading a new
value into CCAPnH. This new value will be shifted into
CCAPnL when CL rolls over from FFH to 00H.
8.2.5 Watchdog Timer
Only Module 4 can be programmed as a Watchdog Timer
(but it can still be programmed to the other modes if the
Watchdog Timer mode is not used). The Watchdog Timer
compares the PCA timer/counter value (CH & CL) with
Module 4’s compare registers (CCAP4H & CCAP4L).
When a match occurs, an internal reset will be generated if
the WDTE bit in CMOD register is set. This internal reset
will not cause the RST pin to be driven high. In order to
hold of the reset the user must periodically change the
compare value so it will never match the PCA timer.
9.0 SECURITY LOCK
The Security Lock protects against software piracy and
prevents the contents of the flash from being read by unau-
thorized parties. It also protects against code corruption
resulting from accidental erasing and programming to the
internal flash memory. There are two different types of
security locks in the device security lock system: Hard Lock
and SoftLock.
9.1 Hard Lock
When Hard Lock is activated, MOVC or IAP instructions
executed from an unlocked or SoftLocked program
address space, are disabled from reading code bytes in
Hard Locked memory blocks (See Table 9-2). Hard Lock
can either lock both flash memory blocks or just lock the 8
KByte flash memory block (Block 1). All External Host and
IAP commands except for Chip-Erase are ignored for
memory blocks that are Hard Locked.
9.2 SoftLock
SoftLock allows flash contents to be altered under a secure
environment. This lock option allows the user to update
program code in the SoftLocked memory block through In-
Application Programming Mode under a predetermined
secure environment. For example, if Block 1 (8K) memory
block is locked (Hard Locked or SoftLocked), and Block 0
(64K for SST89E564RD/SST89V564RD) memory block is
SoftLocked, code residing in Block 1 can program Block 0.
The following IAP mode commands issued through the
command mailbox register, SFCM, executed from a
Locked (Hard Locked or SoftLocked) block, can be oper-
ated on a SoftLocked block: Block-Erase, Sector-Erase,
Byte-Program and Byte-Verify.
In External Host Mode, SoftLock behaves the same as a
Hard Lock.
9.3 Security Lock Status
The three bits that indicate the device security lock
status are located in SFST[7:5]. As shown in Figure 9-
1 and Table 9-1, the three security lock bits control the
lock status of the primary and secondary blocks of
memory. There are four distinct levels of security lock
status. In the first level, none of the security lock bits
are programmed and both blocks are unlocked. In the
second level, although both blocks are now locked and
cannot be programmed, they are available for read
operation via Byte-Verify. In the third level, three differ-
ent options are available: Block 1 Hard Lock / Block 0
SoftLock, SoftLock on both blocks, and Hard Lock on
both blocks. Locking both blocks is the same as Level
©2001 Silicon Storage Technology, Inc.
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