ST10C167-Q3 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST10C167-Q3' PDF : 63 Pages View PDF
ST10R167
VII - INTERRUPT SYSTEM (continued)
Hardware traps are exceptions or error conditions
that arise during run-time. They cause immediate
non-maskable system reaction similar to a stan-
dard interrupt service (branching to a dedicated
vector table location).
The occurrence of a hardware trap is additionally
signified by an individual bit in the trap flag regis-
ter (TFR). Except when another higher prioritized
trap service is in progress, a hardware trap will
interrupt any actual program execution. In turn,
hardware trap services can normally not be inter-
rupted by standard or PEC interrupts.
Table 3 shows all of the possible exceptions or
error conditions that can arise during run-time:
Table 3 : Exceptions or error conditions that can arise during run time
Exception Condit ion
Trap
Flag
Trap
Vector
Vector
Location
Trap
Number
Trap
Priority
Reset Functions:
Hardware Reset
Software Reset
Watchdog Timer Overflow
Class A Hardware Traps:
Non-Maskable Interrupt
Stack Overflow
Stack Underflow
Class B Hardware Traps:
Undefined Opcode
Protected Instruction Fault
Illegal Word Operand
Access
Illegal Instruction Access
Illegal External Bus
Access
Reserved
Software Traps
TRAP Instruction
NMI
STKOF
STKUF
UNDOPC
PRTFLT
ILLOPA
ILLINA
ILLBUS
RESET
RESET
RESET
NMITRAP
STOTRA P
STUTRAP
BTRAP
BTRAP
BTRAP
BTRAP
BTRAP
00’0000h
00’0000h
00’0000h
00’0008h
00’0010h
00’0018h
00’0028h
00’0028h
00’0028h
00’0028h
00’0028h
[2Ch –3Ch]
Any [00’0000h– 00’01FCh]
in steps of 4h
00h
00h
00h
02h
04h
06h
0Ah
0Ah
0Ah
0Ah
0Ah
[0Bh – 0Fh]
Any
[00h – 7Fh]
III
III
III
II
II
II
I
I
I
I
I
Current CPU
Priority
16/63
Share Link: 
