ST10F166 View Datasheet(PDF) - STMicroelectronics
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MFG CO.
'ST10F166' PDF : 62 Pages View PDF
ST10F166
14 GENERAL PURPOSE TIMER (GPT) UNIT
The GPT unit represents a very flexible multifunctional timer counter structure which
may be used for many different time related tasks such as event timing and counting,
pulse width and duty cycle measurements, pulse generation, or pulse multiplication.
The GPT unit incorporates five 16-bit timers which are organized in two separate
modules, GPT1 and GPT2. Each timer in each module may operate independently in
a number of different modes, or may be concatenated with another timer of the same
module.
Each of the three timers T2, T3, T4 of the GPT1 module can be configured individu-
ally for one of three basic modes of operation, which are Timer, Gated Timer, and
Counter Mode. In Timer Mode, the input clock for a timer is derived from the internal
system clock, divided by a programmable prescaler, while Counter Mode allows a
timer to be clocked in reference to external events.
Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the
operation of a timer is controlled by the ’gate’ level on an external input pin. For these
purposes, each timer has one associated port pin (T2IN, T3IN, T4IN) which serves as
gate or clock input. The maximum resolution of the timers in the GPT1 module is 400
ns (@fosc = 40 MHz).
The count direction (up/down) for each timer is programmable by software. For timer
T3, the count direction may additionally be altered dynamically by an external signal
on a port pin (T3EUD) to facilitate functions such as position tracking.
Timer T3 has an output toggle latch (T3OTL) which changes its state on each timer
overflow/underflow. The state of this latch may be output on a port pin (T3OUT) e. g.
for time out monitoring of external hardware components, or may be used internally to
clock timers T2 and T4 for measuring long time periods with high resolution.
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