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ST10F166 View Datasheet(PDF) - STMicroelectronics

Part Name
Description
MFG CO.
ST10F166
ST-Microelectronics
STMicroelectronics ST-Microelectronics
'ST10F166' PDF : 62 Pages View PDF
ST10F166
18.4 A/D Converter Characteristics
VCC = 5 V ± 10 %; VSS = 0 V
TA = 0 to +70 °C for ST10F166/166-16
4.0 V VAREF VCC+0.1 V; VSS-0.1 V VAGND VSS+0.2 V
Parameter
Symbol
Limit Values
min.
max.
Analog input voltage range
Sample time
Conversion time
Total unadjusted error
Internal resistance of reference
voltage source 7)
VAIN SR VAGND
tS CC
tC CC
TUE CC
RAREF CC
VAREF
2 tSC
10 tCC + tS +
4TCL
±3
tCC / 250
- 0.25
Internal resistance of analog
source 7)
ADC input capacitance 7)
VAREF Supply Current
RASRC CC
tS / 500
- 0.25
CAIN CC
50
IREF
5
Unit
V
LSB
k
k
pF
mA
Test Condition
1)
2) 4)
3) 4)
5)
tCC in [ns] 6) 7)
tS in [ns] 2) 7)
7)
Notes:
1) VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in
these cases will be X000H or X3FFH, respectively.
2) During the sample time the input capacitance CI can be charged/discharged by the external source. The
internal resistance of the analog source must allow the capacitors to reach their final voltage level within
tS. After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion
result.
The value for the sample clock is tSC = TCL * 32.
3) This parameter includes the sample time tS, the time for determining the digital result and the time to load
the result register with the conversion result.
The value for the conversion clock is tCC = TCL * 32.
4) This parameter depends on the ADC control logic. It is not a real maximum value, but rather a fixum.
5) TUE is tested at VAREF=5.0V, VAGND=0V, VCC=4.8V. It is guaranteed by design characterization for all
other voltages within the defined voltage range.
6) During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal
resistance of the reference voltage source must allow the capacitors to reach their respective voltage level
within tCC. The maximum internal resistance results from the CPU clock period.
7) Not 100% tested, guaranteed by design characterization.
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