ST10F166
Table 1. Pin Definition and Function
Symbol
NMI
Pin
Number
29
Input (I)
Output (O)
I
Function
Non-Maskable Interrupt Input. A high to low transition at this pin
causes the CPU to vector to the NMI trap routine. When the
PWRDN (power down) instruction is executed, the NMI pin must
be low in order to force the ST10R165 to go into power down
mode. If NMI is high, when PWRDN is executed, the part will con-
tinue to run in normal mode.
If not used, pull NMI high externally.
Address Latch Enable Output. Can be used for latching the ad-
ALE
25
O
dress into external memory or an address latch in the multiplexed
bus modes.
RD
26
O
External Memory Read Strobe. RD is activated for every external
instruction or data read access.
Port 1 is a 16-bit bidirectional I/O port. It is bit-wise programmable
for input or output via direction bits. For a pin configured as input,
P1.0 –
P1.15
30 - 37
40 - 47
I/O
the output driver is put into high-impedance state. Port 1 is used
as the 16-bit address bus (A) in demultiplexed bus modes and
also after switching from a demultiplexed bus mode to a multi-
plexed bus mode..
Port 5 is a 10-bit input-only port with Schmitt-Trigger characteris-
P5.0 –
48 – 53
I
tics. The pins of Port 5 also serve as the (up to 10) analog input
P5.9
56 – 59
I
channels for the A/D converter, where P5.x equals ANx (Analog
input channel x) for ST10F166 & ST10F166-16.
62 – 77
I/O
Port 2 is a 16-bit bidirectional I/O port. It is bit-wise programmable
for input or output via direction bits. For a pin configured as input,
the output driver is put into high-impedance state.
The following Port 2 pins also serve for alternate functions:
P2.0 –
62
I/O
P2.0CC0IOCAPCOM: CC0 Cap.-In/Comp.Out
... ... ...
P2.15
...
75
I/O
P2.13CC13IOCAPCOM: CC13 Cap.-In/Comp.Out,
O
BREQExternal Bus Request Output
76
I/O
P2.14CC14IOCAPCOM: CC14 Cap.-In/Comp.Out,
O
HLDAExternal Bus Hold Acknowl. Output
77
I/O
P2.15CC15IOCAPCOM: CC15 Cap.-In/Comp.Out,
I
HOLDExternal Bus Hold Request Input
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