ST10F167 View Datasheet(PDF) - STMicroelectronics
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MFG CO.
'ST10F167' PDF : 69 Pages View PDF
ST10F167
IX - CAPTURE/COMPARE (CAPCOM) UNIT
The CAPCOM units support generation and con-
trol of timing sequences on up to 32 channels. It
has a maximum resolution of 400ns at 20MHz
CPU clock. The CAPCOM units are typically used
to handle high speed I/O tasks such as pulse and
waveform generation, pulse width modulation
(PMW), Digital to Analog (D/A) conversion, soft-
ware timing, or time recording relative to external
events.
Four 16-bit timers (T0/T1, T7/T8) with reload reg-
isters, provide two independent time bases for the
capture/compare register array.
The input clock for the timers is programmable to
several pre-scaled values of the internal system
clock, or may be derived from an overflow/under-
flow of timer T6 in module GPT2. This provides a
wide range of variation for the timer period and
resolution and allows precise adjustments to
application specific requirements. In addition,
external count inputs for CAPCOM timers T0 and
T7 allow event scheduling for the capture/com-
pare registers relative to external events.
Both of the two capture/compare register arrays
contain 16 dual purpose capture/compare regis-
ters, each of which may be individually allocated
to either CAPCOM timer T0 or T1 (T7 or T8,
respectively), and programmed for capture or
compare function. Each register has one port pin
associated with it which serves as an input pin for
triggering the capture function, or as an output pin
(except for CC24...CC27) to indicate the occur-
rence of a compare event.
When a capture/compare register has been
selected for capture mode, the current contents of
the allocated timer will be latched (‘captured) into
the capture/compare register in response to an
external event at the port pin which is associated
with this register. In addition, a specific interrupt
request for this capture/compare register is gener-
ated. Either a positive, a negative, or both a posi-
tive and a negative external signal transition at the
pin can be selected as the triggering event. The
contents of all registers which have been selected
for one of the five compare modes are continu-
ously compared with the contents of the allocated
timers. When a match occurs between the timer
value and the value in a capture/compare register,
specific actions will be taken, based on the
selected compare mode (see Table 7).
The input frequencies fTx for Tx are determined as
a function of the CPU clocks. The formulas are
detailed in the user manual. The timer input fre-
quencies, resolution and periods which result
from the selected pre-scaler option in TxI when
using a 25MHz CPU clock are listed in the table
below. The numbers for the timer periods are
based on a reload value of 0000H. Note that some
numbers may be rounded to 3 significant figures
(see Table 8).
Table 7 : Compare modes
Compare Modes
Function
Mode 0
Mode 1
Mode 2
Mode 3
Double Register
Mode
Interrupt-only compare mode; several compare interrupts per timer period are possible
Pin toggles on each compare match; several compare events per timer period are possible
Interrupt-only compare mode; only one compare interrupt per timer period is generated
Pin set ‘1’ on match; pin reset ‘0’ on compare time overflow; only one compare event per timer
period is generated
Two registers operate on one pin; pin toggles on each compare match; several compare events
per timer period are possible.
Table 8 : CAPCOM timer input frequencies, resolution and periods
fCPU = 25MHz
Pre-scaler for fCPU
Input Frequency
Resolution
Period
Timer Inpu t Selection TxI
000B
8
2.5MHz
400ns
26.2ms
001B
16
010B
32
1.25MHz
800ns
52.4ms
625KHz
1.60µs
105ms
011B
64
313KHz
3.20µs
210ms
100B
128
156KHz
6.40µs
419ms
101B
256
110B
512
111B
1024
78.1KHz
12.8µs
839ms
39.1KHz
25.6µs
1.68s
19.5KHz
51.2µs
3.36s
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