ST10F168-Q3 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST10F168-Q3' PDF : 74 Pages View PDF
ST10F168
5.2 - Programming Examples
Programming a double Word
; code shown below assumes that Flash is mapped in segment 1
; ie. bit ROMS1 = ‘1’ in SYSCON register
; Flash must be enabled, ie. bit ROMEN = ‘1’ in SYSCON.
MOV R0, #0DD40h ; DD4xh : Double Word programming command
OR
R0, #01h
; Selects segment 1 in flash memory
MOV R1, #00224h ; Address to be programmed is 01’0224h
MOV R2, #03456h ; Data to be programmed at 01’0224h
MOV R3, #04567h ; Data to be programmed at 01’0226h
MOV R4, #050d
; 50ns is 20MHz CPU clock frequency
MOV R7, #08000h ; R7 used for Flash trigger sequence
#define FCR 08000h
; Flash Unlock Sequence consists in two consecutive writes, with the direct
addressing mode and then the indirect addressing mode. FCR must represent an
even address in the active address space of the Flash memory, and Rwn can be
any unused Word GPR (R6 to R15)loaded with a value resulting in the same even
address than FCR
EXTS #1, #2
; Flash can be mapped in segment 0 or 1
MOV FCR, R7
; first part
MOV [R7], R7
; second part
NOP
; WARNING: place 2 NOP operations after
NOP
; the Unlock sequence to avoid all possible
; pipeline conflicts in STEAK programs
Note: For easier coding, the standard data paging addressing scheme is overriden for the two MOV
instructions of the Flash Trigger Sequence (EXTS instruction). However this coding also locks
both standard and PEC interrupts and class A hardware traps. This override can be replaced by
an ATOMIC instruction if the standard DPP addressing scheme must be preserved.
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