ST10F168-Q3 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST10F168-Q3' PDF : 74 Pages View PDF
ST10F168
Table 1 : Pin Description (continued)
Symbol
Pin Type
Function
P1L.0 - P1L.7 118-125
P1H.0 - P1H.7 128-135
132
133
134
135
XTAL1
138
XTAL2
137
RSTIN
140
RSTOUT
141
NMI
142
VAREF
37
VAGND
38
VPP/RPD
84
VDD
VSS
17,46,
56,72,
82,93,
109, 126,
136, 144
18,45,
55,71,
83,94,
110, 127,
139, 143
I/O Two 8-bit bidirectional I/O ports P1L and P1H, bit-wise programmable for input or
output via direction bit. Programming an I/O pin as input forces the corresponding
output driver to high impedance state. Port1 is used as the 16-bit address bus (A) in
demultiplexed bus modes and also after switching from a demultiplexed bus mode
to a multiplexed bus mode.
The following Port1 pins have alternate functions:
I P1H.4 CC24IO CAPCOM2: CC24 Capture Input
I P1H.5 CC25IO CAPCOM2: CC25 Capture Input
I P1H.6 CC26IO CAPCOM2: CC26 Capture Input
I P1H.7 CC27IO CAPCOM2: CC27 Capture Input
I XTAL1 Oscillator amplifier and internal clock generator input
O XTAL2: Oscillator amplifier circuit output.
To clock the device from an external source, drive XTAL1 while leaving XTAL2
unconnected. Minimum and maximum high / low and rise / fall times specified in the
AC Characteristics must be observed.
I Reset Input with Schmitt-Trigger characteristics. A low level at this pin for a speci-
fied duration while the oscillator is running resets the ST10F168. An internal pullup
resistor permits power-on reset using only a capacitor connected to VSS. In bidirec-
tional reset mode (enabled by setting bit BDRSTEN in SYSCON register), the
RSTIN line is pulled low for the duration of the internal reset sequence.
O Internal Reset Indication Output. This pin is set to a low level during hardware, soft-
ware or watchdog timer reset. RSTOUT remains low until the EINIT (end of initial-
ization) instruction is executed.
I Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU to
vector to the NMI trap routine. If bit PWDCFG = ‘0’ in SYSCON register, when the
PWRDN (power down) instruction is executed, the NMI pin must be low in order to
force the ST10F168 to go into power down mode. If NMI is high and PWDCFG =’0’,
when PWRDN is executed, the part will continue to run in normal mode.
If it is not used, pin NMI should be pulled high externally.
- A/D converter reference voltage.
- A/D converter reference ground.
- Flash programming voltage. Programming voltage of the on-chip Flash memory
must be supplied to this pin.
It is used also as the timing pin for the return from interruptible powerdown mode.
-
Digital Supply Voltage:
= + 5V during normal operation and idle mode.
> 2.5V during power down mode.
-
Digital Ground.
9/74
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