ST10F269 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST10F269' PDF : 160 Pages View PDF
ST10F269
Table 3 : Instructions
Instruction Mne Cycle
1st
Cycle
2nd
Cycle
3rd
Cycle
4th Cycle
5th
Cycle
6th
7th
Cycle Cycle
Read/Reset
Addr.1
RD 1+
X2
Read Memory Array until a new write cycle is initiated
Data xxF0h
Read/Reset
RD
3+
Addr.1
Data
x1554h
xxA8h
x2AA8h
xx54h
xxxxxh Read Memory Array until a new write
xxF0h cycle is initiated
Addr.1 x1554h x2AA8h x1554h
Program Word PW 4
Data xxA8h xx54h xxA0h
WA 3
WD 4
Read Data Polling or Tog-
gle bit until Program com-
pletes.
Block Erase
Addr.1 x1554h x2AA8h x1554h x1554h x2AA8h BA
BE 6
BA’ 5
Data xxA8h xx54h xx80h
xxA8h
xx54h xx30h xx30h
Chip Erase
Addr.1 x1554h x2AA8h x1554h x1554h x2AA8h x1554h
CE 6
Note 6
Data xxA8h xx54h xx80h
xxA8h
xx54h xx10h
Erase Suspend ES
1
Addr.1
Data
X2 Read until Toggle stops, then read or program all data needed
xxB0h from block(s) not being erased then Resume Erase.
Erase Resume ER
1
Addr.1
Data
X2 Read Data Polling or Toggle bit until Erase completes or Erase is
xx30h supended another time.
Set Block/Code
Addr.1 x2A54h x15A8h x2A54h Any odd
Protection
word
SP 4
address 9
Data xxA8h xx54h xxC0h
WPR 7
Read
Protection
Status
Addr.1 x2A54h x15A8h x2A54h
Any odd
word Read Protection Register
RP 4
address 9 until a new write cycle is
initiated.
Data xxA8h xx54h xx90h Read PR
Block
Temporary
Unprotection
BTU 4
Addr.1 x2A54h
Data xxA8h
x15A8h
xx54h
x2A54h
xxC1h
X2
xxF0h
Code
Temporary
Unprotection
CTU 1
Addr.1
Data
MEM 8
Write cycles must be executed from Flash.
FFFFh
Code
Temporary
Protection
CTP 1
Addr.1
Data
MEM 8
Write cycles must be executed from Flash.
FFFBh
Notes 1. Address bit A14, A15 and above are don’t care for coded address inputs.
2. X = Don’t Care.
3. WA = Write Address: address of memory location to be programmed.
4. WD = Write Data: 16-bit data to be programmed
5. Optional, additional blocks addresses must be entered within a time-out delay (96 µs) after last write entry, timeout status can be
verified through FSB.3 value. When full command is entered, read Data Polling or Toggle bit until Erase is completed or suspended.
6. Read Data Polling or Toggle bit until Erase completes.
7. WPR = Write protection register. To protect code, bit 15 of WPR must be ‘0’. To protect block N (N=0,1,...), bit N of WPR must be
‘0’. Bit that are already at ‘0’ in protection register must also be ‘0’ in WPR, else a writing error will occurs (it is not possible to write a
‘1’ in a bit already programmed at ‘0’).
8. MEM = any address inside the Flash memory space. Absolute addressing mode must be used (MOV MEM, Rn), and instruction
must be executed from Flash memory space.
9. Odd word address = 4n-2 where n = 0, 1, 2, 3..., ex. 0002h, 0006h...
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