ST10F269-T3 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST10F269-T3' PDF : 160 Pages View PDF
ST10F269-T3
Symbol
Pin Type
Function
P0L.0 - P0L.7, 100-107, I/O Two 8-bit bidirectional I/O ports P0L and P0H, bit-wise programmable for input or
P0H.0
108,
output via direction bit. Programming an I/O pin as input forces the corresponding
P0H.1 - P0H.7 111-117
output driver to high impedance state.
In case of an external bus configuration, PORT0 serves as the address (A) and as
the address / data (AD) bus in multiplexed bus modes and as the data (D) bus in
demultiplexed bus modes.
Demultiplexed bus modes
Data Path Width:
P0L.0 – P0L.7:
P0H.0 – P0H.7
8-bit
D0 – D7
I/O
Multiplexed bus modes
16-bit
D0 - D7
D8 - D15
Data Path Width: 8-bit
16-bit
P0L.0 – P0L.7: AD0 – AD7 AD0 - AD7
P0H.0 – P0H.7 A8 – A15 AD8 - AD15
P1L.0 - P1L.7 118-125
P1H.0 - P1H.7 128-135
I/O Two 8-bit bidirectional I/O ports P1L and P1H, bit-wise programmable for input or
output via direction bit. Programming an I/O pin as input forces the corresponding
output driver to high impedance state. PORT1 is used as the 16-bit address bus (A)
in demultiplexed bus modes and also after switching from a demultiplexed bus mode
to a multiplexed bus mode.
The following PORT1 pins have alternate functions:
132
I P1H.4 CC24IO
CAPCOM2: CC24 Capture Input
133
I P1H.5 CC25IO
CAPCOM2: CC25 Capture Input
134
I P1H.6 CC26IO
CAPCOM2: CC26 Capture Input
135
I P1H.7 CC27IO
CAPCOM2: CC27 Capture Input
XTAL1
138
I XTAL1 Oscillator amplifier and/or external clock input.
XTAL2
137
O XTAL2 Oscillator amplifier circuit output.
To clock the device from an external source, drive XTAL1 while leaving XTAL2
unconnected. Minimum and maximum high / low and rise / fall times specified in the
AC Characteristics must be observed.
RSTIN
140
I Reset Input with Schmitt-Trigger characteristics. A low level at this pin for a specified
duration while the oscillator is running resets the ST10F269-T3. An internal pull-up
resistor permits power-on reset using only a capacitor connected to VSS. In bidirec-
tional reset mode (enabled by setting bit BDRSTEN in SYSCON register), the
RSTIN line is pulled low for the duration of the internal reset sequence.
RSTOUT
141
O Internal Reset Indication Output. This pin is driven to a low level during hardware,
software or watchdog timer reset. RSTOUT remains low until the EINIT (end of ini-
tialization) instruction is executed.
NMI
142
I Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU to
vector to the NMI trap routine. If bit PWDCFG = ‘0’ in SYSCON register, when the
PWRDN (power down) instruction is executed, the NMI pin must be low in order to
force the ST10F269-T3 to go into power down mode. If NMI is high and PWDCFG
=’0’, when PWRDN is executed, the part will continue to run in normal mode.
If not used, pin NMI should be pulled high externally.
VAREF
37
- A/D converter reference voltage.
VAGND
38
- A/D converter reference ground.
RPD
84
- Timing pin for the return from interruptible powerdown mode and synchronous /
asynchronous reset selection.
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