ST10F269Z2QX View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST10F269Z2QX' PDF : 161 Pages View PDF
ST10F269Z2Qx
Table 3 : Instructions
Instruction Mne Cycle
1st
Cycle
2nd
Cycle
3rd
Cycle
4th Cycle
5th
Cycle
6th
7th
Cycle Cycle
Read/Reset
RD 1+
Read/Reset
RD 3+
Program Word PW 4
Block Erase
BE 6
Chip Erase
CE 6
Erase Suspend ES 1
Erase Resume ER 1
Set Block/Code
Protection
SP 4
Read
Protection
Status
RP 4
Block
Temporary
Unprotection
Code
Temporary
Unprotection
Code
Temporary
Protection
BTU 4
CTU 1
CTP 1
Addr.1
Data
Addr.1
Data
Addr.1
Data
Addr.1
Data
Addr.1
Data
Addr.1
Data
Addr.1
Data
Addr.1
Data
Addr.1
Data
Addr.1
Data
X2
Read Memory Array until a new write cycle is initiated
xxF0h
x1554h
xxA8h
x2AA8h
xx54h
xxxxxh Read Memory Array until a new write
xxF0h cycle is initiated
x1554h
xxA8h
x2AA8h
xx54h
x1554h
xxA0h
WA 3
WD 4
Read Data Polling or Toggle
bit until Program completes.
x1554h x2AA8h x1554h x1554h x2AA8h BA
BA’ 5
xxA8h xx54h xx80h
xxA8h
xx54h xx30h xx30h
x1554h
xxA8h
x2AA8h
xx54h
x1554h
xx80h
x1554h
xxA8h
x2AA8h x1554h
Note 6
xx54h xx10h
X2 Read until Toggle stops, then read or program all data needed
xxB0h from block(s) not being erased then Resume Erase.
X2 Read Data Polling or Toggle bit until Erase completes or Erase is
xx30h suspended another time.
x2A54h
x15A8h
x2A54h
Any odd
word
address 9
xxA8h xx54h xxC0h
WPR 7
x2A54h
xxA8h
x15A8h
xx54h
x2A54h
xx90h
Any odd
word
address 9
Read PR
Read Protection Register
until a new write cycle is
initiated.
x2A54h x15A8h x2A54h
X2
xxA8h xx54h xxC1h
xxF0h
Addr.1
Data
MEM 8
Write cycles must be executed from Flash.
FFFFh
Addr.1
Data
MEM 8
Write cycles must be executed from Flash.
FFFBh
Notes 1. Address bit A14, A15 and above are don’t care for coded address inputs.
2. X = Don’t Care.
3. WA = Write Address: address of memory location to be programmed.
4. WD = Write Data: 16-bit data to be programmed
5. Optional, additional blocks addresses must be entered within a time-out delay (96 µs) after last write entry, time-out status can be
verified through FSB.3 value. When full command is entered, read Data Polling or Toggle bit until Erase is completed or suspended.
6. Read Data Polling or Toggle bit until Erase completes.
7. WPR = Write protection register. To protect code, bit 15 of WPR must be ‘0’. To protect block N (N=0,1,...), bit N of WPR mu st be
‘0’. Bit that are already at ‘0’ in protection register must also be ‘0’ in WPR, else a writing error will occurs (it is not possible to write a
‘1’ in a bit already programmed at ‘0’).
8. MEM = any address inside the Flash memory space. Absolute addressing mode must be used (MOV MEM, Rn), and instruction
must be executed from Flash memory space.
9. Odd word address = 4n-2 where n = 0, 1, 2, 3..., ex. 0002h, 0006h...
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