ST10F276 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST10F276' PDF : 229 Pages View PDF
ST10F276
Bootstrap loader
5.4.3
5.4.4
ST10 configuration in CAN BSL
When the ST10F276 enters BSL mode via CAN, the configuration shown in Table 31 is
automatically set (values that deviate from the normal reset values are marked in bold).
Table 31. ST10 configuration in CAN BSL
Function or register
Access
Notes
Watchdog timer
Register SYSCON
Context pointer CP
Register STKUN
Stack pointer SP
Register STKOV
Register BUSCON0
Disabled
0404H (1)
FA00H
FA00H
FA40H
FC00H
acc. to startup
config.(2)
CAN1 Status/Control register 0000H
CAN1 Bit timing register
acc. to ‘0’ frame
XPERCON
P4.6 / CAN1_TxD
042DH
‘1’
DP4.6
‘1’
XPEN bit set
Initialized only if Bootstrap via CAN
Initialized only if Bootstrap via CAN
XRAM1-2, XFlash, CAN1 and XMISC enabled
Initialized only if Bootstrap via CAN
Initialized only if Bootstrap via CAN
1. In Bootstrap modes (standard or alternate) ROMEN, bit 10 of SYSCON, is always set regardless of EA pin
level. BYTDIS, bit 9 of SYSCON, is set according to data bus width selection via Port0 configuration.
2. BUSCON0 is initialized with 0000h, external bus disabled, if pin EA is high during reset. If pin EA is low
during reset, BUSACT0, bit 10, and ALECTL0, bit 9, are set enabling the external bus with lengthened ALE
signal. BTYP field, bit 7 and 6, is set according to Port0 configuration.
Other than after a normal reset, the watchdog timer is disabled, so the bootstrap loading
sequence is not time limited. Pin CAN1_TxD1 is configured as output, so the ST10F276 can
return the identification frame. Even if the internal IFLASH is enabled, a code cannot be
executed from it.
Loading the start-up code via CAN
After sending the acknowledge byte, the BSL enters a loop to receive 128 bytes via CAN1.
Hint: The number of bytes loaded when booting via the CAN interface has been extended to
128 bytes to allow the reconfiguration of the CAN Bit Timing Register with the best timings
(synchronization window, ...). This can be achieved by the following sequence of
instructions:
ReconfigureBaud rate:
MOV R1,#041h
MOV DPP3:0EF00h,R1 ; Put CAN in Init, enable Configuration Change
MOV R1,#01600h
MOV DPP3:0EF06h,R1 ; 1MBaud at Fcpu = 20 MHz
These 128 bytes are stored sequentially into locations 00’FA40H through 00’FABFH of the
IRAM, allowing up to 64 instructions to be placed into the RAM area. To execute the loaded
code the BSL then jumps to location 00’FA40H, that is, the first loaded instruction. The
bootstrap loading sequence is now terminated; however, the ST10F276 remains in BSL
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