ST16C1551 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'ST16C1551' PDF : 37 Pages View PDF
áç
REV. 4.2.0
ST16C1550/51
2.97V TO 5.5V UART WITH 16-BYTE FIFO
FIGURE 16. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED]
TX FIFO
Empty
TX
INT*
TXRDY
(ISR bit-4)
Data in
TX FIFO
Start
Bit
Stop
Bit
S D0:D7 T
S D0:D7 T S D0:D7 T T S D0:D7 T S D0:D7 T
TSI
INT Cleared*
TX FIFO above trigger
level and IER[1] enabled.
TWT
TX FIFO drops
below trigger level
Last Data Byte
Transmitted
S D0:D7 T
TSRT
TX FIFO
Empty
IOW#
(Loading data
into FIFO)
*INT is cleared when the ISR is read and IER[1] is disabled.
TXDMA#
FIGURE 17. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED]
Start
Bit
Stop
Bit
TX
S D0:D7 T S D0:D7 T
INT*
TXRDY
(ISR bit-4)
IOW#
(Loading data
into FIFO)
Last Data Byte
Transmitted
D0:D7 S D0:D7 T
S D0:D7 T S D0:D7 T
S D0:D7 T
TSRT
TSI INT cleared*
TX FIFO above trigger
level and IER[1] enabled.
TX FIFO
Full
TX FIFO drops
below trigger level
At least 1
empty location
in FIFO
TWT
*INT cleared when the ISR is read and IER[1] is disabled.
TXDMA
31
Share Link: 
