ST16C452CJ68PS-F View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'ST16C452CJ68PS-F' PDF : 30 Pages View PDF
ST16C452/452PS
A2 A1 A0
Register
[Default]
Note 5*
BIT-7
BIT-6
Printer Port Register Set: Note 3*
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
[X] 0 0
[X] 0 0
[X] 0 1
PR[00]
PR[00]
SR[4F]
[X] 0 1
[X] 1 0
IOSEL
COM[E0]
[X] 1 0
CON[00]
bit-7
bit-7
-Busy
bit-7
logic
“1”
[X]
bit-6
bit-6
-ACK
bit-6
logic
“1”
[X]
bit-5
bit-5
PE
bit-5
logic
“1”
PD 0-7
IN/OUT
bit-4
bit-4
SLCT
bit-4
-INTP
Enable
-INTP
Enable
bit-3
bit-3
Error
State
bit-3
-SLCTIN
-SLCTIN
bit-2
bit-2
-IRQ
bit-2
INIT
INIT
bit-1
bit-1
logic
“1”
bit-1
-Auto
FDXT
-Auto
FDXT
bit-0
bit-0
logic
“1”
bit-0
-STROBE
-STROBE
Note 1* The General Register set is accessible only when CS A or CS B is a logic 0.
Note 2* The Baud Rate register set is accessible only when CS A or CS B is a logic 0 and LCR bit-7 is a logic 1.
Note 3*: Printer Port Register set is accessible only when -CSP is a logic 0 in conjunction with the states of the
interface signal BIDEN and Printer Control Register bit-5 or IOSEL register.
Note 5* The value between the square brackets represents the register’s initialized HEX value, X = N/A.
UART REGISTER DESCRIPTIONS
Transmit (THR) and Receive (RHR) Holding Reg-
isters
The serial transmitter section consists of an 8-bit
Transmit Hold Register (THR) and Transmit Shift
Register (TSR). The status of the THR is provided in
the Line Status Register (LSR). Writing to the THR
transfers the contents of the data bus (D7-D0) to the
THR, providing that the THR or TSR is empty. The
THR empty flag in the LSR register will be set to a logic
1 when the transmitter is empty or when data is
transferred to the TSR. Note that a write operation can
be performed when the transmit holding register
empty flag is set (logic 0 = Buffer full).
The serial receive section also contains an 8-bit
Receive Holding Register, RHR. Receive data is
removed from the 452/452PS by reading the RHR
register. The receive section provides a mechanism to
prevent false starts. On the falling edge of a start or
false start bit, an internal receiver counter starts
counting clocks at the 16x clock rate. After 7 1/2 clocks
the start bit time should be shifted to the center of the
start bit. At this time the start bit is sampled and if it is
still a logic 0 it is validated. Evaluating the start bit in
this manner prevents the receiver from assembling a
false character. Receiver status codes will be posted
in the LSR.
Rev. 3.20
14
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