ST16C580CP40 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'ST16C580CP40' PDF : 41 Pages View PDF
ST16C580
REGISTER FUNCTIONAL DESCRIPTIONS
The following table delineates the assigned bit functions for the fifteen 580 internal registers. The assigned
bit functions are more fully defined in the following paragraphs.
Table 5, ST16C580 INTERNAL REGISTERS
A2 A1 A0
Register
[Default]
Note *5
BIT-7
BIT-6
BIT-5
General Register Set
0 0 0 RHR [XX]
bit-7
bit-6
bit-5
000
THR [XX]
bit-7
bit-6
bit-5
001
IER [00]
CTS
RTS
Xoff
interrupt interrupt interrupt
010
010
011
100
FCR [00]
ISR [01]
LCR [00]
MCR [00]
RCVR
trigger
(MSB)
FIFO’s
enabled
RCVR
trigger
(LSB)
FIFO’s
enabled
divisor
latch
enable
Clock
select
set
break
IR
enable
TX
trigger
(MSB)
INT
priority
bit-4
set
parity
0
BIT-4
bit-4
bit-4
Sleep
mode
TX
trigger
(LSB)
INT
priority
bit-3
even
parity
loop
back
BIT-3
BIT-2
BIT-1
bit-3
bit-3
modem
status
interrupt
DMA
mode
select
INT
priority
bit-2
parity
enable
-OP2
bit-2
bit-2
receive
line
status
interrupt
XMIT
FIFO
reset
INT
priority
bit-1
stop
bits
-OP1
bit-1
bit-1
transmit
holding
register
RCVR
FIFO
reset
INT
priority
bit-0
word
length
bit-1
-RTS
BIT-0
bit-0
bit-0
receive
holding
register
FIFO
enable
INT
status
word
length
bit-0
-DTR
101
LSR [60]
110
MSR [X0]
FIFO
data
error
CD
trans.
empty
RI
111
SPR [FF]
bit-7
bit-6
Special Register Set: Note *3
000
DLL [XX]
bit-7
bit-6
001
DLM [XX]
bit-15
bit-14
trans.
holding
empty
DSR
bit-5
break
interrupt
CTS
bit-4
framing
error
delta
-CD
bit-3
bit-5
bit-13
bit-4
bit-12
bit-3
bit-11
parity
error
delta
-RI
bit-2
bit-2
bit-10
overrun
error
delta
-DSR
bit-1
receive
data
ready
delta
-CTS
bit-0
bit-1
bit-0
bit-9
bit-8
Rev. 1.20
16
Share Link: 
