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REV. 5.0.0
ST16C650A
2.90V TO 5.5V UART WITH 32-BYTE FIFO
ORDERING INFORMATION
PART NUMBER
ST16C650ACP40
ST16C650ACJ44
ST16C650ACQ48
ST16C650AIP40
ST16C650AIJ44
ST16C650AIQ48
PACKAGE
40-Lead PDIP
44-Lead PLCC
48-Lead TQFP
40-Lead PDIP
44-Lead PLCC
48-Lead TQFP
OPERATING
TEMPERATURE
RANGE
DEVICE STATUS
0°C to +70°C Discontinued. See the ST16C650ACQ48 for a replacement.
0°C to +70°C Active
0°C to +70°C Active
-40°C to +85°C Discontinued. See the ST16C650AIQ48 for a replacement.
-40°C to +85°C Active
-40°C to +85°C Active
PIN DESCRIPTIONS
NAME
40- 44- 48-
PDIP PLCC TQFP
PIN # PIN # PIN #
TYPE
DESCRIPTION
16 (Intel) MODE DATA BUS INTERFACE. The SEL pin is connected to VCC.
A2
26
29
26
I Address bus lines [2:0]
A1
27
30
27
A2:A0 selects internal UART’s configuration registers.
A0
28
31
28
D7
8
9
4
IO Data bus lines [7:0] (bidirectional)
D6
7
8
3
D5
6
7
2
D4
5
6
47
D3
4
5
46
D2
3
4
45
D1
2
3
44
D0
1
2
43
IOR#
21
24
19
I Input/Output Read (active low)
The falling edge instigates an internal read cycle and retrieves the data
byte from an internal register pointed by the address lines [A2:A0], places
it on the data bus to allow the host processor to read it on the leading
edge. Its function is the same as IOR, except it is active low. Either an
active IOR# or IOR is required to transfer data from 650A to CPU during a
read operation. If this input is unused, it should be connected to VCC to
minimize supply current.
IOR
22
25
20
I Input/Output Read (active high)
Same as IOR# but active high. If this input is unused, it should be con-
nected to GND to minimize supply current.
IOW#
18
20
16
I Input/Output Write (active low) - Intel bus mode
The falling edge instigates the internal write cycle and the trailing edge
transfers the data byte on the data bus to an internal register pointed by
the address lines [A2:A0]. Its function is the same as IOW, except it is
active low. Either an active IOW# or IOW is required to transfer data from
650A to the Intel type CPU during a write operation. If this input is unused,
it should be connected to VCC to minimize supply current.
3