ST16C650AIQ48 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'ST16C650AIQ48' PDF : 52 Pages View PDF
ST16C650A
2.90V TO 5.5V UART WITH 32-BYTE FIFO
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REV. 5.0.0
TABLE OF CONTENTS
GENERAL DESCRIPTION .................................................................................................1
FEATURES ...................................................................................................................................................1
APPLICATIONS .............................................................................................................................................1
FIGURE 1. BLOCK DIAGRAM ..................................................................................................................................................................... 1
FIGURE 2. INTEL AND PC MODE PIN OUT ................................................................................................................................................. 2
PIN DESCRIPTIONS ........................................................................................................3
ORDERING INFORMATION ..............................................................................................................................3
1.0 Product Description ............................................................................................................... 7
2.0 FUNCTIONAL DESCRIPTIONS .............................................................................................. 8
2.1 HOST DATA BUS INTERFACE ................................................................................................................ 8
FIGURE 3. ST16C650A INTEL BUS INTERCONNECTIONS.......................................................................................................................... 8
FIGURE 4. ST16C650A MOTOROLA BUS INTERCONNECTIONS. ................................................................................................................. 9
FIGURE 5. ST16C650A PC MODE INTERCONNECTIONS ........................................................................................................................... 9
2.1.1 PC MODE................................................................................................................................................. 10
TABLE 1: PC MODE INTERFACE ON-CHIP ADDRESS DECODER AND INTERRUPT SELECTION. .................................................................... 10
FIGURE 6. PC MODE INTERFACE IN AN EMBEDDED APPLICATION. ........................................................................................................... 10
2.2 5-VOLT TOLERANT INPUTS ................................................................................................................. 11
2.3 DEVICE RESET .................................................................................................................................. 11
2.4 DEVICE IDENTIFICATION AND REVISION ............................................................................................... 11
2.5 DMA MODE ...................................................................................................................................... 11
TABLE 2: TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE .................................................................................................. 11
2.6 INTERRUPT ........................................................................................................................................ 12
TABLE 3: INTERRUPT OUTPUT (INT AND IRQA) FUNCTIONS ................................................................................................................... 12
2.7 CRYSTAL OSCILLATOR OR EXTERNAL CLOCK ...................................................................................... 13
2.8 PROGRAMMABLE BAUD RATE GENERATOR ......................................................................................... 13
FIGURE 7. TYPICAL OSCILLATOR CONNECTIONS ...................................................................................................................................... 13
2.9 TRANSMITTER .................................................................................................................................... 14
FIGURE 8. BAUD RATE GENERATOR....................................................................................................................................................... 14
TABLE 4: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK.............................................................................. 14
2.9.1 Transmit Holding Register (THR) - Write Only ......................................................................................... 15
2.9.2 Transmitter Operation in non-FIFO Mode ................................................................................................ 15
2.9.3 Transmitter Operation in FIFO Mode........................................................................................................ 15
FIGURE 9. TRANSMITTER OPERATION IN NON-FIFO MODE...................................................................................................................... 15
FIGURE 10. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE ........................................................................................... 15
2.10 RECEIVER ....................................................................................................................................... 16
2.10.1 Receive Holding Register (RHR) - Read-Only ....................................................................................... 16
FIGURE 11. RECEIVER OPERATION IN NON-FIFO MODE ......................................................................................................................... 16
2.11 AUTOMATIC RTS (HARDWARE) FLOW CONTROL ............................................................................... 17
2.12 AUTO CTS FLOW CONTROL ............................................................................................................. 17
FIGURE 12. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE ............................................................................... 17
2.13 AUTO XON/XOFF (SOFTWARE) FLOW CONTROL ................................................................................ 18
FIGURE 13. AUTO RTS AND CTS FLOW CONTROL OPERATION .............................................................................................................. 18
2.14 SPECIAL CHARACTER DETECT ......................................................................................................... 19
2.15 AUTO RS485 HALF-DUPLEX CONTROL ............................................................................................ 19
TABLE 5: AUTO XON/XOFF (SOFTWARE) FLOW CONTROL ....................................................................................................................... 19
TABLE 6: RS485 HALF-DUPLEX CONTROL ............................................................................................................................................. 19
2.16 INFRARED MODE ............................................................................................................................. 20
FIGURE 14. INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING ................................................................................. 20
2.17 SLEEP MODE & WAKE-UP INDICATOR ............................................................................................... 21
2.17.1 Sleep Mode in IR Mode .......................................................................................................................... 21
2.18 INTERNAL LOOPBACK ....................................................................................................................... 22
FIGURE 15. INTERNAL LOOP BACK ......................................................................................................................................................... 22
3.0 UART CONFIGURATION REGISTERS ................................................................................. 23
TABLE 7: ST16C650A UART CONFIGURATION REGISTERS .......................................................................................................... 23
TABLE 8: UART CONFIGURATION REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1. .......................... 24
4.0 Internal register descriptions .............................................................................................. 25
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