ST18-AU1 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST18-AU1' PDF : 87 Pages View PDF
ST18-AU1
18.3.1 Clocks electrical characteristics
CLK0
t2
t3
t1
t4
CLKOUT
INCYCLE
t6
t5
CLK1
t8
SCLK(out)
t9
t7
t10
No Parameter
Min (ns) Typ (ns) Max (ns)
t1
CLKOUT rise time
t2
CLKOUT fall time
t3
CLKOUT high delay(1)
7.05
t4
CLKOUT low delay(1)
6.95
t5
INCYCLE high delay
0.55
t6
INCYCLE low delay
T0-0.7
t7
SCLK out rise time
t8
SCLK out fall time
t9
SCLK out high delay(2)
6.25
t9
SCLK out high delay(3)
7.10
t10 SCLK out low delay(2)
6.75
t10 SCLK out low delay(3)
7.70
(1): CLK0_MODE=0 (Bypass PLL)
(2): CLK1_MODE=0 (Bypass PLL),MCLK_MODE=0 (select internal generation from CLK1)
No divide option set.
(3):CLK1_MODE=0 (Bypass PLL),MCLK_MODE=0 (select internal generation from CLK1)
Prescaler divide by 2
72/87
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