ST18952 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST18952' PDF : 67 Pages View PDF
ST18952
ISPR: Interrupt stack pointer register
(Address = 002B, Reset = 0000h, Read/Write)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------------
ISP(2:0)
Bit
ISPR
Function
Number of stacked priority levels (0, 1, 2 or 3)
Note:
’-’ is RESERVED (read: 0, write: don’t care)
ISPR contains the number of stacked priority levels. If the ISPR value is directly written, the
SPLi/CPL values are modified. So the ICR register content is no longer significant but the
interrupt routine procedure is not affected. After reset, ISPR default value is 0
ISR: Interrupt status register
(Address = 002C, Reset = 0000h, Read/Write)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
---
- - - - IPE7 IPE6 IPE5 IPE4 IPE3 IPE2 IPE1 IPE0
Bit
Function
IPE
Interrupt pending bit
0: Reset when interrupt request is acknowledged (default)
1: Set when interrupt request is recorded
Note:
‘-’ is RESERVED (read: 0, write: don’t care)
An interrupt pending (IPE) bit is associated with each interrupt input. IPE is set when the
interrupt request is recorded and is reset when the interrupt request is acknowledged (ITACK
falling edge).
When the user does not want to acknowledge any of the pending interrupt requests, the IPE
flag of the CCR register must first be reset and then the ISR register set to “0000”.
When only some pending interrupt requests need to be acknowledged, the IPE bits of the other
interrupt inputs must be reset.
When the IPE bit is set by a direct register write an interrupt request will be generated
irrespective of the state of the ITRQ pin.
When the mask (IM) bit is set, the corresponding IPE bit is reset.
30/66
Share Link: 
