ST18952
12.1 System registers
There are 4 system registers: CMR clock management register; PICR port/interrupt control
register; INTR interrupt vector register; and DMAR DMA management register. The registers
are Y memory-mapped.
PICR: Port/interrupt control register
The interrupt controller ITRQ inputs can be connected to external interrupt requests or to
internal peripheral requests, this is dependent on the setting of the port/interrupt control (PICR)
system register.
The interrupt controller receives interrupt requests from primary inputs P_ITRQ0-7 on its
inputs ITRQ0-7 when bit 0-7 of the PICR register is set to ‘0’. Otherwise, the ITRQ0-7 input is
connected to the internal peripheral interrupt request output. Each input can be programmed
independently.
(Address = 0049 h, Reset value = 0000 h, Read/Write)
15 14 13 12 11 10 9 8 7 6 5
4
3
2
1
0
NM IO IO TIM1 TIM0 DMA3 DMA2 DMA1 DMA0
Bit
DMA0
DMA1
DMA2
DMA3
TIM0
TIM1
IO
IO
NM
Bits15:9
Function
0: ITC ITRQ0 connected to P_ITRQ0 primary I/O
1: ITC ITRQ0 connected to DMA DIT0 output
0: ITC ITRQ1 connected to P_ITRQ1 primary I/O
1: ITC ITRQ1 connected to DMA DIT1 output
0: ITC ITRQ2 connected to P_ITRQ2 primary I/O
1: ITC ITRQ2 connected to DMA DIT2 output
0: ITC ITRQ3 connected to P_ITRQ3 primary I/O
1: ITC ITRQ3 connected to DMA DIT3 output
0: ITC ITRQ4 connected to P_ITRQ4 primary I/O
1: ITC ITRQ4 connected to TIMER0 interrupt request output
0: ITC ITRQ5 connected to P_ITRQ5 primary I/O
1: ITC ITRQ5 connected to TIMER1 interrupt request output
0: ITC ITRQ6 connected to P_ITRQ6 primary I/O
1: ITC ITRQ6 is not used (connected to VDD)
0: ITC ITRQ7 connected to P_ITRQ7 primary I/O
1: ITC ITRQ7 is not used (connected to VDD)
0: Normal mode.
1: ITC inhibited (bit 7-0 UNUSED).
D950Core IT input directly connected to P_ITRQ-7 primary I/O.
UNUSED
Note: P_ITRQ0-7 primary I/Os are used for external interrupt requests and for the D950 8-bit
general purpose parallel port (P0-7). Depending on the PICR value and the programming of
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