ST18AU1_DS View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST18AU1_DS' PDF : 87 Pages View PDF
ST18-AU1
Table 2.11 D950-Core control (3 pins)
Pin name
RESET
LP
MODE_RESET
Type
I
I
I
Description
Reset input. Active low.
Initializes the 950-Core to the Reset state.
Low power input. Active low.
Mode selection for Reset.
When low, forces reset address to 0x0000.
When high, forces reset address to 0xFC00.
Table 2.12 Emulation unit (4 pins)
Pin name
ERQ
IDLE
HALTACK
SNAP
Type
I
O
O
O
Description
Emulator halt request. Active low.
Halts program execution and enters emulation mode.
Output flag asserted high when the processor is halted due to an emulation
halt request or a valid breakpoint condition.Asserted low when the proces-
sor is not Halted or during execution of an instruction under control of the
emulator.
Halt acknowledge. Active high.
Asserted high when the processor is halted from an Emulator Halt request
or when a valid Breakpoint condition is met.
Snapshot. Active high.
Asserted high when executing an instruction if Snapshot mode is enabled.
Table 2.13 JTAG IEEE 1149.1 test access port(5 pins)
Pin name
TDI
TCK
TMS
TDO
TRST
Type
I
I
I
O
I
Description
Test data input.
Test clock.
Test mode select.
Test data output.
Test logic reset (also used for Emulator module). Active low.
11/87
Share Link: 
