ST18AU1_DS View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST18AU1_DS' PDF : 87 Pages View PDF
18.3.10 I2S Data Input 0
ST18-AU1
CLKDIN0
WSDIN0
DIN0
DREQ0
t 90 t91
t92 t93
t90 t91
t92 t93
t90 t91
t92 t93
t90 t91
t92 t93
t94
t95
t94
t95
SLAVE MODE
CLK1
t96
t97
t97
t96
CLKDIN0
t98
t99
t98
t99
WSDIN0
t100t101
t100t101
DIN0
t102
DREQ0
t102
t102
t102
MASTER MODE
No
PARAMETER
t90
WSDIN0 to CLKDIN0 setup time
t91
CLKDIN0 to WSDIN0 hold time
t92
DIN0 to CLKDIN0 setup time
t93
CLKDIN0 to DIN0 hold time
t94
CLKDIN0 to DREQ0 rise propagation time
t95*
CLK0 rise to DREQ0 fall propagation time
t96
CLK1 rise to CLKDIN0 fall propagation time
t97
CLK1 rise to CLKDIN0 rise propagation time
t98
CLK1 rise to WSDIN0 fall propagation time
t99
CLK1 rise to WSDIN0 rise propagation time
t100 DIN0 to CLK1 rise setup time
t101 CLK1 rise to DIN0 hold time
t102 CLK1 rise to DREQ0 propagation time
* For this time, CLKDIN0 is halted by DREQ0.
Min (ns)
Typ (ns)
-1.45
2.10
-2.95
3.45
7.05
12.90
9.70
9.90
11
10.95
-4.80
-5.40
10.90
Max (ns)
81/87
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