ST18D952 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST18D952' PDF : 67 Pages View PDF
ST18952
requests from primary inputs P_ITRQ0-7 on its inputs ITRQ0-7 when bit 0-7 of the PICR
register is set to ‘0’. Otherwise, the ITRQ0-7 input is connected to internal peripheral interrupt
request output. Each input can be programmed independently.
8.1 Interrupt controller registers
The interrupt controller interface is controlled by status and control registers mapped into the
Y-memory space. Status registers are not write-protected.
IVO0-7: Interrupt vector0-7 address registers
The IVO0-7 registers (one per external interrupt) contain the first address of the interrupt
routine and are associated with the respective interrupt input ITRQ0-7. The register content of
the interrupt under service is provided on the YD bus during the cycle following the ITACK
falling edge.
(Address = 0020-0027, No reset value, Read/Write)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IVi 15 IVi 14 IVi 13 IVi 12 IVi 11 IVi 10 IVi 9 IVi 8 IVi 7 IVi 6 IVi 5 IVi 4 IVi 3 IVi 2 IVi 1 IVi 0
ICR: Interrupt control register
The ICR register displays the current priority level and up to four stacked priority levels.
(Address = 0028, Reset = 000Bh, Read/Write))
15 14 13 12 11 10 9 8 7
SPL4 (2:0)
SPL3 (2:0)
SPL2 (2:0)
65 4
SPL1 (2:0)
32 1 0
ES
CPL (2:0)
Bit
CPL
ES
SPL1
SPL2
SPL3
SPL4
Function
Current priority level (-1, 0, 1, 2 or 3) (default is 011)
Empty stack flag
0: stack is used
1: stack is not used (default)
3-bit 1st stacked priority level
3-bit 2nd stacked priority level
3-bit 3rd stacked priority level
3-bit 4th stacked priority level
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