ST20-C1 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST20-C1' PDF : 205 Pages View PDF
4.4 Arithmetic
section 4.7, and the general principles of expression evaluation are described in
section 4.3.
4.4.1 Addition, subtraction and multiplication
Single length signed arithmetic is provided by the operations listed in Table 4.4.
Mnemonic
Name
adc n
add constant
add
add
sub
subtract
mul
multiply
smul
short multiply
Table 4.4 Single length signed integer arithmetic instructions
Each of these instructions except smul can signal overflow or underflow by setting the
appropriate bit in the status register. An overflow occurs if the result is greater than
MostPos and an underflow if it is less than MostNeg. If overflow or underflow occurs,
then the 32 least significant bits of the full result are left in the Areg. The overflow and
underflow are ‘sticky’, so when one has been set, it is not cleared and the other cannot
be set by subsequent arithmetic. The overflow and underflo w bits may be used for
saturated arithmetic, as described in section 4.4.3.
The primary instruction adc n adds the constant value n to Areg. Breg and Creg are
unaffected. This is used for incrementing and decrementing variables and counters.
If op is one of add, sub, mul or smul, then the instruction sequence
ldl X; ldl Y; op;
evaluates the expression
X op Y
i.e. it takes the value in Breg as the left hand operand and the value in Areg as the
right hand operand, and loads the result into Areg. The content of Creg is popped into
Breg and the initial Areg is rotated into Creg.
smul multiples two half-word values producing a 32-bit result. It cannot overflow or
underflow and is faster than mul.
4.4.2 Division and remainder
Division and remainder are performed using the operations listed in Table 4.5.
Mnemonic
Name
divstep
divide step
unsign
unsign argument
Table 4.5 Division and remainder instructions
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