ST20-C1 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST20-C1' PDF : 205 Pages View PDF
1.1 ST20-C1 features
1 Introduction
This manual provides a summary and reference to the ST20 architecture and instruc-
tion set for the ST20-C1 core.
ST20 is a technology for building successful embedded VLSI designs. ST20 devices
comprise a collection of VLSI macro-cells connected through a high-performance on-
chip bus. This architecture allows the easy construction of both general purpose (e.g.
ST20-MC1 micro-controller) and application specific devices (e.g. ST20-TPx digital
set top box family).
The ST20 macro-cell library includes CPU micro-cores, on-chip memories and a wide
range of digital and analogue I/O devices. SGS-THOMSON offers a range of ST20
CPU micro-cores, allowing the best cost vs. performance trade-off to be achieved in
each application area. This manual describes the ST20-C1 CPU micro-core.
ST20 devices are available from SGS-THOMSON and licensed second source
vendors.
1.1 ST20-C1 features
The ST20-C1 has the following features:
• It is implemented as a 2-way superscalar, 3-stage pipeline, with an internal 16-
word register cache. This architecture can sustain 4 instructions in progress,
with a maximum of 2 instructions completing per cycle.
• It uses a variable length instruction coding scheme based on 8-bit units which
gives excellent static and dynamic code size. Instructions take between 1 and
8 units to code, with an average of 1.25 units (10 bits) per instruction.
• It provides flexible prioritized vectored interrupt capabilities. The worst case
interrupt latency is 0.5 microseconds (at 33 Mhz operating frequency).
• It provides extensive instruction level support for 16-bit digital signal process-
ing (DSP) algorithms.
• It is particularly suitable for low power and battery-powered applications, with
low core operating power, and sophisticated power management facilities.
• It provides extensive real-time debugging capability through the optional ST20
diagnostic controller unit (DCU) macro-cell, which supports fully non-intrusive
breakpoints, watchpoints and code tracing.
• It has a flexible and powerful built-in hardware scheduler. This is a light-weight
real-time operating system (RTOS) directly implemented in the microcode of
the ST20-C1 processor. The hardware scheduler can be customized and pro-
vides support for software schedulers.
• It provides a built-in user-programmable 32-bit input/output register providing
system control and communication capability directly from the CPU.
4/205
®
Share Link: 
