ST40RA166 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST40RA166' PDF : 88 Pages View PDF
ST40RA166
5 Clock generation
CLOCKGENA.FRQCR and
CLOCKGENB.FRQCR
ST40RA166 codified ratios
Clock ratios
Lower 9 bit
0x02C
0x048
0x04A
0x04C
0x05A
0x05C
0x063
0x06C
0x091
0x093
0x0A3
0x0DA
0x0DC
0x0EC
0x123
0x16C
Available
on start up
CPU_
CLK
1/2
BUS_
CLK
1/2
1/2
PER_
CLK
1/8
1/4
1/6
1/8
CPU_ BUS_ PER_
CLK CLK CLK
1
1/2
1/8
1
1
1/2
1
1
1/3
1
1
1/4
1/3
1/6
1
2/3
1/6
MODE7
1/2
1/4
1/2
1/4
1
1/2
1/2
1/8
1
1/2
1/4
1/3
1/3
1/6
1
1
1/2
1/6
1
1/2
1/2
1/4
1
1
1/2
1/4
1/8
1/4
1/8
1/8
1
1
1
Table 17: Valid FRQCR values and their ratios
1/2
1/2
1
1/2
1/2
1/2
5.4.1
Programming the PLL output frequency
The three dividers used within the PLL are referred to as M (predivider), N (feedback divider) and P
(postdivider) for brevity. Note that there is a divide-by-2 fixed prescaler before the feedback divider.
The binary values applied to the programmable dividers, and the frequency of CLOCKIN controls the
output frequency of the PLL macrocell:
F(clockout)
=
---2-----×-----N-----
M × 2P
×
F
(
cloc
kin
)
where the values of M, N and P must satisfy the following constraints:
q Divider limits: 1 ≤ M ≤ 255, 1 ≤ N ≤ 255, 0 ≤ P ≤ 5 ,
q
Phase
comparator
limits:
1MHz
≤
F----(---c---l--o----c---k----i-n----)
M
≤
2MHz
,
q
VCO
limit:
200MHz
≤
2-----M×-----N---
×
F(clockin) ≤
622MHz ,
q M divider limit: F(clockin) ≤ 200MHz· .
For example, if 300 MHz from an input clock of 33 MHz is to be generated, the values of M, N and
P are worked out as below.
34/88
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