ST40RA166 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST40RA166' PDF : 88 Pages View PDF
5 Clock generation
ST40RA166
1 The phase comparator must operate between 1 MHz and 2 MHz, so choose M = 22 (for
1.5 MHz operation).
2 The VCO needs to run between 200 MHz and 622 MHz. It could be run at 300 MHz directly
(which takes a little less current), or at 600 MHz then divide by 2 to ensure an exact 50% duty
cycle. In this example 600 MHz is chosen so N = 200.
3 The postdivider then needs to be a divide by 2. This is programmed in powers of 2, so P = 1.
The P divider changes value without glitching of the output clock.
5.4.2
Changing clock frequency
The clock frequencies are changed in two ways.
q Change the core PLL frequencies.
The PLL must be stopped, the control register reconfigured with the new settings, and the PLL
restarted at the new frequency.
q Change the frequency division ratio of the clock domains.
The control registers are changed dynamically and the new frequencies are effective
immediately.
5.4.3
Changing the core PLL frequencies
This procedure applies to either CLOCKGENA or CLOCKGENB and to PLL1 or PLL2.
1 Stop the PLL. The CLOCKGENA.PLL1CR2.STBPLLENSEL register selects whether the PLL is
enabled by the CLOCKGENA.PLL1CR2.STBPLLEN or the CPG.FRQCR.PLL1EN register.
2 Reconfigure the PLL. Set the CLOCKGENA.PLL1CR1 register to one of the supported
configurations on the datasheet.
3 Restart the PLL, following the procedure described in the ST40 System Architecture Volume 1:
System.
5.4.4
Changing the frequency division ratio
The frequency division ratio is selected by changing the CPG.FRQCR register for PLL1 or the
CLOCKGENA.PLL2_MUXCR register for PLL2. This change is immediately effective.
5.5 Power management
The power management unit (PMU) is responsible for clock startup and shutdown for each of the
on-chip modules. Power is conserved by powering down those modules which are not in use, or
even the CPU itself.
The PMU is operated using three banks of registers as follows:
q CPG: controls the power-down mode of the CPU and the power-down states of the legacy
on-chip peripherals,
q CLOCKGENA and CLOCKGENB: control the power-down states of the other on-chip peripherals.
5.5.1
CPU low-power modes
The CPU can be put into sleep or standby modes. In sleep mode the CPU is halted while the
on-chip peripherals continue to operate. In standby mode all the on-chip peripherals are stopped
along with the CPU. In addition, the on-chip peripherals can be independently stopped.
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