ST40RA166
6.4 LMI interface (SDRAM) AC specifications
6 Electrical specifications
LCLKOUTA
LCLKOUTB
Outputs
Tri-state outputs
Inputs
tLCHLCH
tLCHLCL
tLCLLCH
tLCLLOV
tLCHLON
tLCHLOZ
tLCHLIX
tLIVLCH
Figure 11: LMI SDRAM mode timings
Symbol
tLCHLCH
tLCHLCL
tLCLLCH
tLCHLOV
tLCHLOZ
tLCHLON
tLIVLCH
tLCHLIX
Parameter
Min
LMI clock period
LMI clock high time
LMI clock low period
LCLKOUT low to output signals valid
LCLKOUT high to outputs tri-state
LCLKOUT high to outputs on
Input signals valid to LCLKOUT high
Input signals hold after LCLKOUT high
10
0.45
0.45
-1.5
0
-2
1
2
Table 25: LMI SDRAM AC timings
Max
0.5
2
Units
ns
tLCHLCH
tLCHLCH
ns
ns
ns
ns
ns
Note
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