ST40RA166 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST40RA166' PDF : 88 Pages View PDF
ST40RA166
6 Electrical specifications
Symbol
Parameter
Min
Max
Units Note
tLCLLCH
tLCHLAV
tLCHDQSR
tDQSH
tDQSL
tDQSRS
tDQSRH
tLCHDQS
LMI clock low period
LCLKOUT low to address and command valid
LCLKOUT high to read DQS edge
DQS high
DQS low
Read data setup for DQS edge
Read data hold for DQS edge
LCLKOUT high to write DQS
tLDWS
Write data setup to DQS edge
tLDWH
DQS edge to Write data invalid
tLCHDWZ LCLKOUT high to write data Z
0.45
-1.5
-1.5
0.45
0.45
1 - tLCHLCH / 4
tLCHLCH / 4 + 1
N * tLCHLCH / 4 -
0.75
N * tLCHLCH / 4 -
0.75
N * tLCHLCH / 4 +
0.75
tLCHLCH
1.5
ns
1.5
ns
a
tLCHLCH
tLCHLCH
ns
a
ns
a
N * tLCHLCH / ns
4 + 0.75
ns
ns
2
ns
Table 26: LMI DDR-SDRAM AC timings
a. Constraint placed on external system
6.6 DDR bus termination (SSTL_2)
The JEDEC specification for SSTL_2 and an application note from a DDR SDRAM manufacturer
(DDR SDRAM Signaling Design Notes (MIcron Technology)) recommend the following layout to
reduce signal reflections on the bus:
DDR
RS
DDR
RS
RS
RT
VTT
VTT = 1.25 V (VDD / 2)
RS = 27 Ω
RT = 27 Ω
Figure 13: SSTL_2 bus termination
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