ST40RA166 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST40RA166' PDF : 88 Pages View PDF
7 Pin description
ST40RA166
Mode
pin
MODE7
MODE8
Pin name
EADDR9
EADDR10
MODE9
EADDR11
MODE11:1
0
EADDR12
EADDR13
MODE12
MODE13
EADDR14
EADDR15
Architecture Block
signal name affected
MD7
EMISS
MD8
System
MD9
EMI
MD11:10
EMI
MD12
MD13
EMI
Reserved
Description
Enable MPX arbiter
Set endianess
H: Little
L: Big
Set EMI port
H: Master
L: Slave
Set booting ROM bus size
00: Reserved
01: 32-bit
10: 16-bit
11: 8-bit
Enable NOP when accessing flash
Tie high
Notes
b
c
d
MODE14
EADDR16
MD14
PCI
PCI bridge mode
H: Host
L: Satellite
MODE15
EADDR17
MD15
PCI
Reserved: PCI select clock
e
H: External
L: Internal
MODE16
EADDR18
MD16
-
Reserved: Tie high
f
MODE17
EADDR19
MD17
-
MODE18
EADDR20
MD18
-
MODE19
EADDR21
MD19
-
Table 33: Mode selection pins for ST40RA166
a. See CLOCKGEN chapter of the ST40 System Architecture Manual for details.
b. ST40RA166 is always the clock master, providing EMI clocks to the system.
c. See EMI chapter of the ST40 System Architecture Manual for details.
d. reserved for enable retiming stage on EMI padlogic
e. PCI clock is selected externally on the board for ST40RA166. The mode pin may be used for clock
selection in future variants.
f. These mode pins are not used in current variants, however, they may be used to enable additional
functionality in future variants
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