ST486DX View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST486DX' PDF : 8 Pages View PDF
ST 486 DX ASIC CORE
A range of bus master/bus slave/bus monitor
VHDL models are also available for high level 486
bus debug operations.
SYHTHESIS AND STATIC TIMING ANALYSIS
evaluates delays using operating condition
information, input slope conditions and estimated
(pre-layout) parasitic capacitance or calculated
(post-layout) parasitic resistance and capacitance.
The output is in SDF format that can be annotated
Figure 4. Design Flow
BUS / MASTER MODEL
BUS FUNCTIONAL MODEL
MODEL SOURCE HARDWARE MODEL
486 Views
VHDL / Verilog
VHDL/
Verilog
VHDL / Verilog
Co-simulation
Cadence
Leapfrog
TEST COMPILER
SYNOPSYS
SDF
B E H AV IO U RA L
HDL
RTL HDL
LOGIC SYNTHESIS
SYNOPSYS
FLOORPLAN
MANAG ER
VHDL / Verilog
GATE LEVEL SIMULATION
Verilog Netlist
TSSI
BLOCK LEVEL AND CHIP
LEVEL PLACE AND ROUTE
CELL 3
FLOOR PLANNING
SDF
DELAY EVALUATION AND
CLOCK TREE SYNTHESIS
Wire Loads
& Placement data
The Synopsys Design Compiler synthesis tool
family can be used for gate level synthesis and
static timing analysis. Interface to the back end
place and route engine allows for design specific
wire load models to be used during the synthesis
phase. Synopsys library views for the standard cell
libraries and high-level functional modules (such
as the ST486DX core) are used to perform static
timing analysis at block level, intra-block level and
at the top chip level.
Usage of Synopsys Test Compiler enables the
insertion of full or partial scan and also IEEE
JTAG boundary scan insertion.
DELAY EVALUATION AND GATE LEVEL
SIMUATION
All cell timing information used for gate level
simulation and static timing analysis will be
generated by the SGS-Thomson proprietary delay
evaluator called EARLY. This suite of programs
into the gate level simulator and static timing
analysis tool.
Place and Route
This is performed on a module by module basis,
and then at the top level using the Cadence cell 3
layout tool. Interface to floorplanning tools (e.g.
Preview, ChipPlanner) will allow customisable wire
load models to be passed back to the synthesis
environment and also help in the reduction of
routing congestion which leads to smaller die size
and fewer iterations of the design post-layout.
6/8
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