
ST62T55B ST62T65B/E65B
SERIAL PERIPHERAL INTERFACE SPI(Cont’d)
4.6 SPI Timing Diagrams
Figure 27. CPOL = 0 Clock Polarity Normal, CPHA = 0 Phase Selection Normal
SPRUN
SCK
Sin
Sampling
Sout
b7
b6
b5
b4
b3
b2
b1
Figure 28. CPOL = 1 Clock Polarity Inverted, CPHA = 0 Phase Selection Normal
b0
VR001694
SPRUN
SCK
Sin
Sampling
Sout
b7
b6
b5
b4
b3
b2
b1
b0
VR0A1694
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