ST6255C ST6265C ST6265B
1 GENERAL DESCRIPTION
1.1 INTRODUCTION
The ST6255C, and ST6265C devices are low cost
members of the ST62xx 8-bit HCMOS family of mi-
crocontrollers, which is targeted at low to medium
complexity applications. All ST62xx devices are
based on a building block approach: a common
core is surrounded by a number of on-chip periph-
erals.
The ST62E65C is the erasable EPROM version of
the ST62T65C OTP device, which may be used to
emulate the ST62T55C and ST62T65C OTP de-
vices, as well as the respective ST6255C and
ST6265C ROM devices.
OTP and EPROM devices are functionally identi-
cal. The ROM based versions offer the same func-
tionality selecting as ROM options the options de-
jFigure 1. Block Diagram
fined in the programmable option byte of the OTP/
EPROM versions.
OTP devices offer all the advantages of user pro-
grammability at low cost, which make them the
ideal choice in a wide range of applications where
frequent code changes, multiple code versions or
last minute programmability are required.
These compact low-cost devices feature a Timer
comprising an 8-bit counter and a 7-bit program-
mable prescaler, an 8-bit Auto-Reload Timer,
EEPROM data capability (except ST62T55C), a
serial port communication interface, an 8-bit A/D
Converter with 13 analog inputs and a Digital
Watchdog timer, making them well suited for a
wide range of automotive, appliance and industrial
applications.
TEST/VPP
NMI
TEST
8-BIT
A/D CONVERTER
INTERRUPT
PROGRAM
MEMORY
3884 bytes
(ST62T55C, T65C,
E65C)
DATA ROM
USER
SELECTABLE
DATA RAM
128 Bytes
DATA EEPROM
128 Bytes
(ST62T65C/E65C)
PC
STACK LEVEL 1
STACK LEVEL 2
STACK LEVEL 3
STACK LEVEL 4
STACK LEVEL 5
STACK LEVEL 6
8 BIT CORE
POWER
SUPPLY
OSCILLATOR
RESET
PORT A
PORT B
PORT C
AUTORELOAD
TIMER
TIMER
SPI (SERIAL
PERIPHERAL
INTERFACE)
DIGITAL
WATCHDOG
PA0..PA7 / Ain
PB0..PB5 / 30 mA Sink
PB6 / ARTimin / 30 mA Sink
PB7 / ARTimout / 30 mA Sink
PC0 / Ain
PC1 / Tim1 / Ain
PC2 / Sin / Ain
PC3 / Sout / Ain
PC4 / Sck / Ain
VDD VSS OSCin OSCout RESET
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