ST6255C ST6265C ST6265B
SERIAL PERIPHERAL INTERFACE SPI (Cont’d)
4.5.2 SPI Timing Diagrams
Figure 31. CPOL = 0 Clock Polarity Normal, CPHA = 0 Phase Selection Normal
SPRUN
SCK
Sin
Sampling
Sout
b7
b6
b5
b4
b3
b2
b1
Figure 32. CPOL = 1 Clock Polarity Inverted, CPHA = 0 Phase Selection Normal
b0
VR001694
SPRUN
SCK
Sin
Sampling
Sout
b7
b6
b5
b4
b3
b2
b1
b0
VR0A1694
56/84