ST62T35B/E35B
CLOCK SYSTEM (Cont’d)
Figure 11. Clock Circuit Block Diagram
POR
MAIN
OSCILLATOR
OSG
LFAO
: 13
Core
TIMER 1
M
U
fINT
: 12
Watchdog
X
M
U ADC
:6
X
:1
ARTIMER 16
Main Oscillator off
Figure 12. Maximum Operating Frequency (fMAX) versus Supply Voltage (VDD)
Maximum FREQUENCY (MHz)
8
7
6
4
5
4
3
fOSG
2
fOSG Min
3
2
1
1
2.5
3
3.5
4
4.5
5
5.5
6
SUPPLY VOLTAGE (VDD)
VR01807
Notes:
1. In this area, operation is guaranteed at the
quartz crystal frequency.
2. When the OSG is disabled, operation in this
area is guaranteed at the crystal frequency. When
the OSG is enabled, operation in this area is guar-
anteed at a frequency of at least fOSG Min.
3. When the OSG is disabled, operation in this
area is guaranteed at the quartz crystal frequency.
When the OSG is enabled, access to this area is
prevented. The internal frequency is kept a Of SG.
4. When the OSG is disabled, operation in this
area is not guaranteed
When the OSG is enabled, access to this area is
prevented. The internal frequency is kept at Of SG.
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