ST62T35B/E35B
1 GENERAL DESCRIPTION
1.1 INTRODUCTION
The ST62T35B and ST62E35B devices are low
cost members of the ST62xx 8-bit HCMOS family
of microcontrollers, which is targeted at low to me-
dium complexity applications. All ST62xx devices
are based on a building block approach: a com-
Figure 1. Block Diagram
mon core is surrounded by a number of on-chip
peripherals.
The ST62E35B is the erasable EPROM version of
the ST62T35B device, which may be used to em-
ulate the ST62T35B device, as well as the respec-
tive ST6235B ROM devices.
TEST/ VPP
NMI
T EST
8-BIT
A/D CONVERTER
INTERRUPT
PRO GRAM
Memory
79 48 bytes
DATA ROM
USER
SELEC TABLE
DATA RAM
192 Bytes
DATA EEPROM
128 Bytes
PC
STACK LEVEL 1
STACK LEVEL 2
STACK LEVEL 3
STACK LEVEL 4
STACK LEVEL 5
STACK LEVEL 6
8 BIT CORE
POWER
SUP PLY
OSCILLATOR
RESE T
PORT A
PORT B
PORT C
PORT D
UAR T
PORT E
AUTORELOAD
TIMER
TIM ER
SPI (SERIA L
PERIPHER AL
INTERF ACE)
DIGI TAL
WATCHDO G
PA0..PA1 / 20 mA Sink
PA2/OVF/ 20 mA Sink
PA3/PWM/20 mA Sink
PA4/Ain/CP 1
PA 5/Ain/CP2
PA 6...PA7/Ain
PB 0..PB7/Ain
PC4..PC7/Ain
PD0,PD 6,PD7/Ain
PD1/Ain/Scl
PD2/Ain/Si n
PD3/Ain/Sout
PD4/Ain/R XD1
PD5/Ain/TX D1
PE0...PE7
TIMER
VDDVSS OSCin OSCout RESE T
(VPP on EPROM/OTP versions only)
VR01823E
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