ST63126 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST63126' PDF : 86 Pages View PDF
ST63140,142,126,156
MEMORY SPACES (Continued)
Data RAM/EEPROM/OSD RAM Addressing
In all members of the ST631xx family 64 bytes of
data RAM are directly addressable in the data
space from 80h to BFh addresses. The additional
192 bytes of RAM, the 128 bytes of EEPROM , and
the OSD RAM can be addressed using the banks
of 64 bytes located between addresses 00h and
3Fh. The selection of the bank is done by program-
ming the Data RAM Bank Register (DRBR) located
at the E8h address of the Data Space. In this way
each bank of RAM, EEPROM or OSD RAM can se-
lect 64 bytes at a time. No more than one bank
should be set at a time.
Figure 16. Data RAM Bank Register
DRBR
Data RAM
Bank Register
(E8h, Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
DRBR0 = Data RAM Bank 0
DRBR1= Data RAM Bank 0
DRBR2= Data RAM Bank 0
DRBR3= Data RAM Bank 0
DRBR4= Data RAM Bank 0
DRBR5= Data RAM Bank 0
DRBR6= Data RAM Bank 0
UNUSED
D7. This bit is not used.
DRBR6, DRBR5. Each of these bits, when set, will
select one OSD RAM register page.
DRBR4,DRBR3,DRBR2. Each of these bits, when
set, will select one RAM page.
DRBR1,DRBR0. These bits select the EEPROM
pages.
This register is undefined after reset. Neither
read nor single bit instructions may be used to
address this register.
Table 5 summarizes how to set the Data RAM
Bank Register in order to select the various banks
or pages.
Note :
Care is required when handling the DRBR as it is
write only. For this reason, it is not allowed to
change the DRBR contents while executing inter-
rupts drivers, as the driver cannot save and than
restore its previous content. If it is impossible to
avoid the writing of this register in interrupts driv-
ers, an image of this register must be saved in a
RAM location, and each time the program writes
the DRBR it writes also the image register.
The image register must be written first, so if an in-
terrupt occurs between the two instructions the
DRBR is not affected.
Table 5. Data RAM Bank Register Set-up
Hex.
01h
02h
04h
08h
10h
20h
40h
DRBR Value
Binary
0000 0001
0000 0010
0000 0100
000 1000
0001 0000
0010 0000
0100 0000
Selection
EEPROM Page 0
EEPROM Page 1
RAM Page 2
RAM Page 3
RAM Page 4
OSD Page 5
OSD Page 6
14/82
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