ST6369 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST6369' PDF : 71 Pages View PDF
ST6369
INTERRUPT (Continued)
Interrupt Procedure
The interrupt procedure is very similar to a call pro-
cedure; the user can consider the interrupt as an
asynchronous call procedure. As this is an asyn-
chronous event the user does not know about the
context and the time at which it occurred. As a re-
sult the user should save all the data space regis-
ters which will be used inside the interrupt routines.
There are separate sets of processor flags for nor-
mal, interrupt and non-maskable interrupt modes
which are automatically switched and so these do
not need to be saved.
The following list summarizes the interrupt proce-
dure (refer also to Figure 19. Interrupt Processing
Flow Chart):
- Interrupt detection
- The flags C and Z of the main routine are ex-
changed with the flags C and Z of the interrupt
routine (resp. the NMI flags)
- The value of the PC is stored in the first level of
the stack - The normal interrupt lines are inhib-
ited (NMI still active)
- The edge flip-flop is reset
- The related interrupt vector is loaded in the PC.
- User selected registers are saved inside the in-
terrupt service routine (normally on a software
stack)
- The source of the interrupt is found by polling
(if more than one source is associated to the
same vector)
- Interrupt servicing
- Return from interrupt (RETI)
- Automatically the ST63xx core switches back
to the normal flags (resp the interrupt flags)
and pops the previous PC value from the stack
The interrupt routine begins usually by the identifi-
cation of the device that has generated the inter-
rupt request. The user should save the registers
which are used inside the interrupt routine (that
holds relevant data) into a software stack.
After the RETI instruction execution, the Core car-
ries out the previous actions and the main routine
can continue.
ST6369 Interrupt Details
IR Interrupt (#0). The IRIN/PC6 Interrupt is con-
nected to the first interrupt #0 (NMI, 0FFCH). If the
IRINT interrupt is disabled at the Latch circuitry,
then it will be high. The #0 interrupt input detects a
Figure 19. Interrupt Processing Flow-Chart
INST RUCT ION
FE TCH
INST RUCTION
EX ECUTE
INST RUCTION
WA S
NO
THE INST RUCTION
A RETI
Y ES
YE S
IS THE CORE
?
ALREADY IN
NORMAL MODE ?
NO
CLEA R
INTERRUPT MAS K
LOAD PC FROM
INTERRUPT VECTOR
( FF C / FFD )
SET
INTE RRUPT MAS K
PUSH THE
PC INTO THE STAC K
S E LEC T
PROGRAM FLA GS
SEL ECT
INTERNAL MODE FLAG
” POP ”
THE STACK ED PC
NO
?
CHECK IF THERE IS
AN INTERRUPT REQUES T
AND INTE RRUPT MASK
YES
VA000014
high to low level. Note that once #0 has been
latched, then the only way to remove the
latched #0 signal is to service the interrupt. #0
can interrupt the other interrupts. A simple latch
is provided from the PC6(IRIN) pin in order to
generate the IRINT signal. This latch can be trig-
gered by either the positive or negative edge of
IRIN signal. IRINT is inverted with respect to the
latch. The latch can be read by software and re-
set by software.
17/67
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