ST6391 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'ST6391' PDF : 68 Pages View PDF
ST6391,92,93,95,97,99
HARDWARE ACTIVATED DIGITAL WATCHDOG
FUNCTION (Continued)
Figure 39. Watchdog Register
HWDR
Hardware Activated Watchdog Register
(D8h, Read/ Write)
D7 D6 D5 D4 D3 D2 D1 D0
C = Watchdog Activation Bit
SR = Software Reset Bit
T1-T6 = Counter Bits
T1-T6. These are the watchdog counter bits. It
should be noted that D7 (T1) is the LSB of the
counter and D2 (T6) is the MSB of the counter,
these bits are in the opposite order to normal.
SR. This bit is set to one during the reset phase
and will generate a software reset if cleared to
zero.
C. This is the watchdog activation bit that is hard-
ware set. The watchdog function is always acti-
vated independently of changes of value of this bit.
The register reset value is FEh (Bit 1-7 set to one,
Bit 0 cleared).
SERIAL PERIPHERAL INTERFACE
The ST639x Serial Peripheral Interface (SPI) has
been designed to be cost effective and flexible in
interfacing the various peripherals in TV applica-
tions.
It maintains the software flexibility but adds hard-
ware configurations suitable to drive devices which
require a fast exchange of data. The three pins
dedicated for serial data transfer (single master
only) can operate in the following ways:
- as standard I/O lines (software configuration)
- as S-BUS or as I2CBUS (two pins)
- as standard (shift register) SPI
When using the hardware SPI, a fixed clock rate of
62.5kHz is provided.
It has to be noted that the first bit that is output on
the data line by the 8-bit shift register is the MSB.
SPI Data/Control Registers
For I/O details on SCL (Serial Clock), SDA (Serial
Data) and SEN (Serial Enable) please refer to I/O
Ports description with reference to the following
registers:
Port C data register, Address C2h (Read/Write).
- BIT D0 “SCL”
- BIT D1 “SDA”
- BIT D3 “SEN”
Port C data direction register, Address C6h
(Read/Write).
Figure 40. SPI Serial Data Register
SSDR
SPI Serial Data Register
(CCh, Read/ Write)
D7 D6 D5 D4 D3 D2 D1 D0
D0-D7 = Data Bits
D7-D0. These are the SPI data bits. They can be
neither read nor written when SPI is operating
(BUSY bit set). They are undefined after reset.
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